A substrate treatment method for treating a substrate, includes the steps of: (A) heating the substrate having a coating film formed on a surface thereof by supply of a coating solution; (B), after the (A) step, moving a discharge destination of a removing solution from a peripheral position on the surface of the substrate toward a center side of the substrate and turning it back at a first position to return it again to the peripheral position while rotating the substrate; (C), after the (B) step, moving the discharge destination of the removing solution from the peripheral position on the surface of the substrate toward center side of the substrate and turning it back at a second position closer to an outside than the first position to return it again to the peripheral position while rotating the substrate; and (D), after the (C) step, heating again the substrate.

A coating technique and a priming material are provided. In an exemplary embodiment, the coating technique includes receiving a substrate and identifying a material of the substrate upon which a layer is to be formed. A priming material is dispensed on the material of the substrate, and a film-forming material is applied to the priming material. The priming material includes a molecule containing a first group based on an attribute of the substrate material and a second group based on an attribute of the film-forming material. Suitable attributes of the substrate material and the film-forming material include water affinity and degree of polarity and the first and second groups may be selected to have a water affinity or degree of polarity that corresponds to that of the substrate material and the film-forming material, respectively.

Methods are presented for forming multi-threshold field effect transistors. The methods generally include depositing and patterning an organic planarizing layer to protect underlying structures formed in a selected one of the nFET region and the pFET region of a semiconductor wafer. In the other one of the nFET region and the pFET region, structures are processed to form an undercut in the organic planarizing layer. The organic planarizing layer is subjected to a reflow process to fill the undercut. The methods are effective to protect a boundary between the nFET region and the pFET region.

A method for transferring a thin layer onto a destination substrate having a face with an adhesive layer includes formation of a polymer material interface layer on a second face of a thin layer, opposite a first face on which an adhesive is present. The method also includes assembly by gluing the interface layer and the adhesive layer and separation of the thin layer relative to a temporary support.

A method and corresponding spin coater is provided for forming a layer of uniform thickness on a semiconductor wafer having a central region and an outer edge. The method includes: depositing a flowable coating material on the semiconductor wafer at the central region, the layer being formed from the coating material; rotating the semiconductor wafer about an axis such that a centrifugal force urges the coating material to spread from the central region toward the outer edge of the semiconductor wafer; and creating a pressure differential in one or more regions proximate to the outer edge of the semiconductor wafer. The pressure differential may be created by a wall with pins holes, the wall at least partially encircling the outer edge of the semiconductor wafer.

Ultra-compact inductor devices for use in integrated circuits (e.g., RF ICs) that use 3-dimensional Dirac materials for providing the inductor. Whereas inductors currently require significant real estate on an integrated circuit, because they require use of an electrically conductive winding around an insulative core, or such metal deposited in a spiral geometry, the present devices can be far more compact, occupying significantly less space on an integrated circuit. For example, an ultra-compact inductor that could be included in an integrated circuit may include a 3-dimensional Dirac material formed into a geometric shape capable of inductance (e.g., as simple as a stripe or series of stripes of such material), deposited on a substantially non-conductive (i.e., insulative) substrate, on which the Dirac material in the selected geometric shape is positioned. Low temperature manufacturing methods compatible with CMOS manufacturing are also provided.

A composition for use in selective modification of a base material surface includes a polymer having, at an end of a main chain or a side chain thereof, a group including a first functional group capable of forming a bond with a metal, and a solvent.

A method of patterning a substrate. The method may include providing a cavity in a layer, disposed on the substrate, the cavity having a first length along a first direction and a first width along a second direction, perpendicular to the first direction, and wherein the layer has a first height along a third direction, perpendicular to the first direction and the second direction. The method may include depositing a sacrificial layer over the cavity in a first deposition procedure; and directing angled ions to the cavity in a first exposure, wherein the cavity is etched, and wherein after the first exposure, the cavity has a second length along the first direction, greater than the first length, and wherein the cavity has a second width along the second direction, no greater than the first width.

A pattern forming material is configured to use for forming an organic film on a film to be processed, patterning the organic film, and then forming a composite film by infiltrating a metallic compound into the patterned organic film. The pattern forming material contains a polymer including a monomer unit represented by a general formula (3) described below,

##STR00001##

where R.sup.21 is H or CH.sub.3, each R.sup.22 is a hydrocarbon group of C.sub.2-14 where a carbon is primary carbon, secondary carbon or tertiary carbon, Q is a single bond or a hydrocarbon group of C.sub.1-20 carbon atoms which may include an oxygen atom, a nitrogen atom, or a sulfur atom between carbon-carbon atoms of or at a bond terminal, and a halogen atom may be substituted for the hydrogen atom.

A method includes forming a gate structure and an interlayer dielectric (ILD) layer over a substrate; selectively forming an inhibitor over the gate structure; performing an atomic layer deposition (ALD) process to form a dielectric layer over the ILD layer, wherein in the ALD process the dielectric layer has greater growing rate on the ILD than on the inhibitor; and performing an atomic layer etching (ALE) process to etch the dielectric layer until a top surface of the inhibitor is exposed, in which a portion of the dielectric layer remains on the ILD layer after the ALE process is complete.