A method is provided for etching a dielectric layer covering a top and a flank of a three-dimensional structure, the method including: a first etching of the dielectric layer, including: a first fluorine-based compound and oxygen, the first etching being performed to: form a first protective layer on the top and form a second protective layer on the dielectric layer, a second etching configured to remove the second protective layer while retaining a portion of the first protective layer, the first and the second etchings being repeated until removing the dielectric layer located on the flank of the structure, and before deposition of the dielectric layer, a formation of an intermediate protective layer between the top and the dielectric layer.

An isolated gate field effect transistor and the manufacture method thereof. The isolated gate field effect transistor includes a substrate; a nitride transistor structure arranged on the substrate; a dielectric layer on the nitride transistor structure, where the dielectric layer includes a first dielectric layer, a second dielectric layer and a third dielectric layer and material of the second dielectric layer includes metal; a groove formed in a gate region and at least partially through the dielectric layer; a metal gate formed in the groove; and a source electrode and a drain electrode located at two ohmic contact regions.

There is provided a film forming method comprising an organic substance removal step of removing an organic substance adhering to an oxide film generated on a surface of a base by supplying a hydrogen-containing gas and an oxygen-containing gas to the base; an oxide film removal step of removing the oxide film formed on the surface of the base after the organic substance removal step; and a film forming step of forming a predetermined film on the surface of the base after the oxide film removal step.

According to an embodiment, a semiconductor memory device comprises: control gate electrodes stacked above a substrate; a semiconductor layer that extends in a first direction above the substrate and faces the control gate electrodes; and a gate insulating layer provided between these control gate electrode and semiconductor layer. The gate insulating layer comprises: a first insulating layer covering a side surface of the semiconductor layer; a charge accumulation layer covering a side surface of this first insulating layer; and a second insulating layer including a metal oxide and covering a side surface of this charge accumulation layer. The charge accumulation layer has: a first portion facing the control gate electrode; and a second portion facing a region between control gate electrodes adjacent in the first direction and including more oxygen than the first portion.

A method for manufacturing a semiconductor structure is provided, which may include: forming a p-doped region adjacent to an n-doped region in a substrate; carrying out an anodic oxidation to form an oxide layer on a surface of the substrate, wherein the oxide layer in a first portion of the surface extending along the n-doped region has a greater thickness than the oxide layer in a second portion of the surface extending along the p-doped region.

A semiconductor process including the following steps is provided. An epitaxial layer is formed on a substrate. An oxide layer is formed on the epitaxial layer, wherein the oxide layer includes a chemical oxide layer, a high-temperature oxide (HTO) layer or a surface modification oxide layer. An ion implant process is performed to the epitaxial layer to form a doped region in the epitaxial layer. The oxide layer is removed by using a diluted hydrofluoric acid (DHF) solution after performing the ion implant process, wherein a volume ratio of water to a hydrofluoric acid (HF) in the DHF solution is 200:1 to 1000:1.

Provided are: forming an oxycarbonitride film, an oxycarbide film or an oxide film on a substrate by alternately performing a specific number of times: forming a first layer containing the specific element, nitrogen and carbon, on the substrate, by alternately performing a specific number of times, supplying a first source containing the specific element and a halogen-group to the substrate in a processing chamber, and supplying a second source containing the specific element and an amino-group to the substrate in the processing chamber; and forming a second layer by oxidizing the first layer by supplying an oxygen-containing gas, and an oxygen-containing gas and a hydrogen-containing gas to the substrate in the processing chamber.

A method for fabricating a semiconductor device includes: forming a mold structure including a mold layer and a supporter layer over a semiconductor substrate; forming an opening penetrating the mold structure; forming a protective layer on a bottom surface and a sidewall of the opening; forming a lower electrode over the protective layer; selectively etching the supporter layer to form a supporter that supports the lower electrode; removing the mold layer to define a non-exposed portion and an exposed portion of an outer wall of the protective layer; and selectively trimming the exposed portion of the protective layer to form a protective layer pattern between the supporter and the lower electrode.

A semiconductor device includes a semiconductor layer of a first conductivity type. A well region that is a second conductivity type well region is formed on a surface layer portion of the semiconductor layer and has a channel region defined therein. A source region that is a first conductivity type source region is formed on a surface layer portion of the well region. A gate insulating film is formed on the semiconductor layer and has a multilayer structure. A gate electrode is opposed to the channel region of the well region where a channel is formed through the gate insulating film.

Embodiments of three-dimensional (3D) memory devices with an enlarged joint critical dimension and methods for forming the same are disclosed. In an example, a 3D memory device is disclosed. The 3D memory device includes a substrate, a memory stack having a plurality of interleaved conductor layers and dielectric layers on the substrate, and a memory string extending vertically through the first memory stack and having a memory film along a sidewall of the memory string. The memory film includes a discontinuous blocking layer interposed by the dielectric layers.