A fin-type field-effect transistor device includes a substrate, insulators, gate stacks and dielectric strips. The substrate includes a first doped region, a second doped region, third doped blocks located above the first doped region and fourth doped blocks located above the second doped region, and fins located above the third doped blocks and the fourth doped blocks, wherein doping concentrations of the third doped blocks are lower than a doping concentration of the first doped region, and doping concentrations of the fourth doped blocks are lower than a doping concentration of the second doped region. The insulators are disposed on the third doped blocks and the fourth doped blocks of the substrate and covering the fins. The dielectric strips are disposed in between the fins, and in between the third doped blocks and the fourth doped blocks. The gate stacks are disposed over the fins and above the insulators.

Embodiments of methods and structures for forming a 3D integrated wiring structure are disclosed. The method can include forming an insulating layer on a front side of a first substrate; forming a semiconductor layer on a front side of the insulating layer; patterning the semiconductor layer to expose at least a portion of a surface of the insulating layer; forming a plurality of semiconductor structures over the front side of the first substrate, wherein the semiconductor structures include a plurality of conductive contacts and a first conductive layer; joining a second substrate with the semiconductor structures; performing a thinning process on a backside of the first substrate to expose the insulating layer and one end of the plurality of conductive contacts; and forming a conductive wiring layer on the exposed insulating layer.

A method of forming a semiconductor device includes forming a gate electrode in a wafer. The formation of the gate electrode includes depositing a work-function layer, after the work-function layer is deposited, performing a treatment on the wafer, wherein the treatment is performed by soaking the wafer using a silicon-containing gas; after the treatment, forming a metal capping layer over the work-function layer; and depositing a filling metal over the metal capping layer.

A method for manufacturing a semiconductor device includes: forming a first film on a substrate; forming a second film containing at least carbon on the first film; forming a hole in the second film; and forming a recess, which communicates with the hole, in the first film by etching using the second film as a mask. In this method, the second film includes a first layer formed on the first film, and a second layer formed on the first layer. The first layer having a higher oxygen concentration than the second layer.

A memory device and a method for fabricating the memory device are provided. The memory device includes a substrate having an upper surface; a stacked structure disposed on the upper surface of the substrate, wherein the stacked structure includes a first insulating layer, a first conductive layer, a second insulating layer, a second conductive layer and a third insulating layer sequentially stacked on the substrate; a plurality of channel structures penetrating the stacked structure and electrically connected to the substrate, wherein each of the channel structures includes an upper portion corresponding to the second conductive layer and a lower portion corresponding to the first conductive layer; a memory layer disposed between the second conductive layer and the upper portion; and a plurality of isolation structures penetrating the stacked structure to separate the stacked structure into a plurality of sub-stacks.

According to one aspect of the technique of the present disclosure, there is provided a seal structure capable of sealing a space between a first structure heated by a heater and a second structure arranged so as to face the first structure, the seal structure including: a metal plate arranged in contact with the first structure; and a sealing material made of a resin material and arranged in contact with the metal plate and the second structure, wherein the space between the first structure and the second structure is sealed by the metal plate and the sealing material.

A semiconductor structure and a method of fabricating the semiconductor structure are provided. The semiconductor structure includes a substrate; a metal gate structure on the substrate; and a spacer next to the metal gate structure having a skirting part extending into the metal gate structure and contacting the substrate. The metal gate structure includes a high-k dielectric layer and a metal gate electrode on the high-k dielectric layer.

Implementations of the disclosed subject matter provide an organic vapor jet print die including a linear array of depositors, with each of the depositors having a cluster of apertures. The organic vapor jet print die may include at least one first aperture in each cluster of apertures is a delivery aperture that is in fluid communication with a carrier gas source and an evaporation oven. At least one second aperture in each cluster of apertures may be an exhaust aperture in fluid communication with a vacuum reservoir with a static pressure lower than that at the apertures. The delivery apertures and exhaust apertures may have a uniformity that is less than 0.4%.

According to one embodiment, a semiconductor memory device includes a stacked body including a plurality of electrode members and a plurality of insulating members, each of the electrode members and each of the insulating members being stacked alternately in a first direction on the substrate. The semiconductor memory device also includes a memory hole that extends in the stacked body in the first direction and a semiconductor member that is disposed to extend in the memory hole in the first direction. The semiconductor memory device also includes a memory member that is disposed between the semiconductor member and the plurality of electrode members. The plurality of electrode members including a first electrode member and a second electrode member, a thickness of the memory member at the position of the first electrode member being greater than a thickness of the memory member at the position of the second electrode member.

A semiconductor storage device includes a substrate, a first conductor layer, a plurality of second conductor layers, and a first contact. The substrate includes a core region, a first region surrounding the core region, and a second region connecting the core region and the first region. The first conductor layer is above the core region, the first region, and the second region. The second conductor layers are above the first conductor layer above the core region. The first contact is above the first region and extends in the thickness direction. The first contact separates the first conductor layer above the first region into a first portion surrounded by the first contact and a second portion surrounding the first contact. The first portion of the first conductor layer includes a first oxidized portion, and the second portion of the first conductor layer includes a second oxidized portion.