A method of forming a high-κ dielectric cap layer on a semiconductor structure formed on a substrate includes depositing the high-κ dielectric cap layer on the semiconductor structure, depositing a sacrificial silicon cap layer on the high-κ dielectric cap layer, performing a post cap anneal process to harden and densify the as-deposited high-κ dielectric cap layer, and removing the sacrificial silicon cap layer.

Provided is a memory device including a substrate, a plurality of word-line structures, a plurality of cap structures, and a plurality of air gaps. The word-line structures are disposed on the substrate. The cap structures are respectively disposed on the word-line structures. A material of the cap structures includes a nitride. The nitride has a nitrogen concentration decreasing along a direction near to a corresponding word-line structure toward far away from the corresponding word-line structure. The air gaps are respectively disposed between the word-line structures. The air gaps are in direct contact with the word-line structures. A method of forming a memory device is also provided.

In certain embodiments, a method for processing a semiconductor substrate includes receiving a semiconductor substrate that includes a film stack. The film stack includes first and second germanium-containing layers and a first silicon layer positioned between the first and second germanium-containing layers. The method includes selectively etching the first silicon layer by exposing the film stack to a plasma that includes fluorine agents and nitrogen agents. The plasma etches the first silicon layer, and causes a passivation layer to be formed on exposed surfaces of the first and second germanium-containing layers to inhibit etching of the first and second germanium-containing layers during exposure of the film stack to the plasma.

A method of forming a semiconductor device is proposed. The method includes providing a semiconductor structure. The method further includes forming an auxiliary layer directly on a part of the semiconductor structure. Silicon and nitrogen are main components of the auxiliary layer. The method further includes forming a conductive material on the auxiliary layer. The conductive material incudes AlSiCu, AlSi or tungsten, and is electrically connected to the part of the semiconductor structure via the auxiliary layer.

A semiconductor device structure is provided. The semiconductor device structure includes a substrate and a gate structure over the substrate. The semiconductor device structure also includes a spacer element covering a first sidewall of the gate structure. The semiconductor device structure further includes a source/drain portion in the substrate, and the spacer element is between the source/drain portion and the gate structure. In addition, the semiconductor device structure includes an etch stop layer covering the source/drain portion. The etch stop layer includes a first nitride layer covering the source/drain portion and having a second sidewall, and the second sidewall is in direct contact with the spacer element. The etch stop layer also includes a first silicon layer covering the first nitride layer and having a third sidewall, and the third sidewall is in direct contact with the spacer element.

Some embodiments include device having a gate spaced from semiconductor channel material by a dielectric region, and having nitrogen-containing material directly against the semiconductor channel material and on an opposing side of the semiconductor channel material from the dielectric region. Some embodiments include a device having a gate spaced from semiconductor channel material by a dielectric region, and having nitrogen within at least some of the semiconductor channel material. Some embodiments include a NAND memory array which includes a vertical stack of alternating insulative levels and wordline levels. Channel material extends vertically along the stack. Charge-storage material is between the channel material and the wordline levels. Dielectric material is between the channel material and the charge-storage material. Nitrogen is within the channel material. Some embodiments include methods of forming NAND memory arrays.

Embodiments disclosed herein relate generally to forming an effective metal diffusion barrier in sidewalls of epitaxy source/drain regions. In an embodiment, a structure includes an active area having a source/drain region on a substrate, a dielectric layer over the active area and having a sidewall aligned with the sidewall of the source/drain region, and a conductive feature along the sidewall of the dielectric layer to the source/drain region. The source/drain region has a sidewall and a lateral surface extending laterally from the sidewall of the source/drain region, and the source/drain region further includes a nitrided region extending laterally from the sidewall of the source/drain region into the source/drain region. The conductive feature includes a silicide region along the lateral surface of the source/drain region and along at least a portion of the sidewall of the source/drain region.

A method of forming a high-K dielectric cap layer on a semiconductor structure formed on a substrate includes depositing the high-K dielectric cap layer on the semiconductor structure, depositing a sacrificial silicon cap layer on the high-K dielectric cap layer, performing a post cap anneal process to harden and densify the as-deposited high-K dielectric cap layer, and removing the sacrificial silicon cap layer.

Embodiments of the present disclosure generally relate to inductively coupled plasma sources, plasma processing apparatus, and independent temperature control of plasma processing. In at least one embodiment, a method includes introducing a process gas into a gas injection channel and generating an inductively coupled plasma within the gas injection channel. The plasma includes at least one radical species selected from oxygen, nitrogen, hydrogen, NH and helium. The method includes delivering the plasma from the plasma source to a process chamber coupled therewith by flowing the plasma through a separation grid between the plasma source and a substrate. The method includes processing the substrate. Processing the substrate includes contacting the plasma including the at least one radical species with a first side of the substrate facing the separation grid and heating the substrate using a plurality of lamps located on a second side of the substrate opposite the separation grid.

In certain embodiments, a method for processing a semiconductor substrate includes receiving a semiconductor substrate that includes a film stack. The film stack includes a first silicon layer, a second silicon layer, and a first germanium-containing layer positioned between the first silicon layer and the second silicon layer. The method further includes selectively etching the first germanium-containing layer by exposing the film stack to a plasma that includes fluorine agents, nitrogen agents, and hydrogen agents. The plasma etches the first germanium-containing layer and causes a passivation layer to be formed on exposed surfaces of the first silicon layer and the second silicon layer to inhibit etching of the first silicon layer and the second silicon layer during exposure of the film stack to the plasma.