Provided is a memory device including a substrate, a plurality of word-line structures, a plurality of cap structures, and a plurality of air gaps. The word-line structures are disposed on the substrate. The cap structures are respectively disposed on the word-line structures. A material of the cap structures includes a nitride. The nitride has a nitrogen concentration decreasing along a direction near to a corresponding word-line structure toward far away from the corresponding word-line structure. The air gaps are respectively disposed between the word-line structures. The air gaps are in direct contact with the word-line structures. A method of forming a memory device is also provided.

In certain embodiments, a method of processing a semiconductor substrate includes positioning a semiconductor substrate in a plasma chamber of a plasma tool. The semiconductor substrate includes a film stack that includes silicon layers and germanium-containing layers in an alternating stacked arrangement, with at least two silicon layers and at least two germanium-containing layers. The method includes exposing, in a first plasma step executed in the plasma chamber, the film stack to a first plasma. The first plasma is generated from first gases that include nitrogen gas, hydrogen gas, and fluorine gas. The method includes exposing, in a second plasma step executed in the plasma chamber, the film stack to a second plasma. The second plasma is generated from second gases comprising fluorine gas and oxygen gas. The second plasma selectively etches the silicon layers.

A method of forming a high-κ dielectric cap layer on a semiconductor structure formed on a substrate includes depositing the high-κ dielectric cap layer on the semiconductor structure, depositing a sacrificial silicon cap layer on the high-κ dielectric cap layer, performing a post cap anneal process to harden and densify the as-deposited high-κ dielectric cap layer, and removing the sacrificial silicon cap layer.

A semiconductor device includes a semiconductor layer of a first conductivity type. A well region that is a second conductivity type well region is formed on a surface layer portion of the semiconductor layer and has a channel region defined therein. A source region that is a first conductivity type source region is formed on a surface layer portion of the well region. A gate insulating film is formed on the semiconductor layer and has a multilayer structure. A gate electrode is opposed to the channel region of the well region where a channel is formed through the gate insulating film.

A semiconductor device includes a semiconductor layer of a first conductivity type. A well region that is a second conductivity type well region is formed on a surface layer portion of the semiconductor layer and has a channel region defined therein. A source region that is a first conductivity type source region is formed on a surface layer portion of the well region. A gate insulating film is formed on the semiconductor layer and has a multilayer structure. A gate electrode is opposed to the channel region of the well region where a channel is formed through the gate insulating film.

The present invention provides a method for the formation of graphene on a silicon substrate, the method comprising: (i) providing a silicon wafer having a growth surface which is free of native oxides, in a reaction chamber; (ii) nitriding the growth surface with a nitrogen-containing gas with the wafer at a temperature in excess of 800° C., to thereby form a silicon nitride layer; and (iii) forming a graphene mono-layer or multiple layer structure on the silicon nitride layer; wherein the method is performed in-situ and sequentially in the reaction chamber. The present invention also provides a graphene-on-silicon layer structure having an intervening silicon nitride layer and free of any intervening native oxide layer.

A method for fabricating a semiconductor device includes providing a substrate including a cell region and a core/peripheral region around the cell region, forming a gate insulating film on the substrate of the core/peripheral region, forming a first conductive film of a first conductive type on the gate insulating film, forming a diffusion blocking film within the first conductive film, the diffusion blocking film being spaced apart from the gate insulating film in a vertical direction, after forming the diffusion blocking film, forming an impurity pattern including impurities within the first conductive film, diffusing the impurities through a heat treatment process to form a second conductive film of a second conductive type and forming a metal gate electrode on the second conductive film, wherein the diffusion blocking film includes helium (He) and/or argon (Ar).

A method of manufacturing a semiconductor structure includes: etching a substrate according to a hard mask to form a plurality of trenches in the substrate; performing a nitridation treatment on the trenches of the substrate; filling the trenches of the substrate with a flowable isolation material; and solidifying the flowable isolation material to form an isolation material. A semiconductor structure manufactured by the method is also provided.

A method of nitridation includes cyclically performing the following steps in situ within a processing chamber at a temperature less than about 400° C.: treating an unreactive surface of a substrate in the processing chamber to convert the unreactive surface to a reactive surface by exposing the unreactive surface to an energy flux, and nitridating the reactive surface using a nitrogen-based gas to convert the reactive surface to a nitride layer including a subsequent unreactive surface.

A semiconductor manufacturing apparatus according to an embodiment includes: a chamber that houses a semiconductor substrate; and a plurality of coils provided on a lateral surface of the chamber. The chamber has a first spatial region enclosed above the semiconductor substrate by a first coil that is one of the plurality of coils, a first gas introduction port communicating with the first spatial region, a second spatial region enclosed by a second coil that is different from the first coil among the plurality of coils, and a second gas introduction port communicating with the second spatial region.