A substrate oxidation assembly includes: a chamber body defining a processing volume; a substrate support disposed in the processing volume; a plasma source coupled to the processing volume; a steam source fluidly coupled to the processing volume; and a substrate heater. A method of processing a semiconductor substrate includes: initiating conformal radical oxidation of high aspect ratio structures of the substrate comprising: heating the substrate; and exposing the substrate to steam; and conformally oxidizing the substrate. A semiconductor device includes a silicon and nitrogen containing layer; a feature formed in the silicon and nitrogen containing layer having an aspect ratio of at least 40:1; and an oxide layer on the face of the feature having a thickness in a bottom region of the silicon and nitrogen containing layer that is at least 95% of a thickness of the oxide layer in a top region.

A method of manufacturing a semiconductor device includes: preparing a substrate processing apparatus including a substrate process chamber having a plasma-generation space where a nitrogen-containing gas is plasma-exited and a process space where a substrate is mounted in communication with the plasma-generation space, an inductive coupling structure configured by a coil and an impedance matching circuit, wherein electric field combining the coil and the circuit has a length of an integer multiple of a wavelength of an high-frequency power, and a table to mount the substrate under a lower end of the coil; mounting the substrate on the table; supplying the nitrogen-containing gas into the chamber; starting a plasma excitation of the nitrogen-containing gas by applying the high-frequency power to the coil; and nitriding a surface of the substrate with active species containing a nitrogen element at an internal pressure of the chamber ranging from 1 to 100 Pa.

A vertical fin field effect transistor including a doped region in a substrate, wherein the doped region has the same crystal orientation as the substrate, a first portion of a vertical fin on the doped region, wherein the first portion of the vertical fin has the same crystal orientation as the substrate and a first portion width, a second portion of the vertical fin on the first portion of the vertical fin, wherein the second portion of the vertical fin has the same crystal orientation as the first portion of the vertical fin, and the second portion of the vertical fin has a second portion width less than the first portion width, a gate structure on the second portion of the vertical fin, and a source/drain region on the top of the second portion of the vertical fin.

The invention describes a method for forming spacers (152a, 152b) of a field effect transistor gate, comprising a step of forming a protection layer (152) covering the gate of said transistor, at least a step of modifying the protection layer, executed after the step of forming the protection layer, by contacting the protection layer (152) with plasma comprising ions heavier than hydrogen and CxHy where x is the proportion of carbon and y is the proportion of hydrogen to form a modified protection layer (158) and a carbon film (271). The protection layer being nitride (N)-based and/or silicon (Si)-based and/or carbon (C)-based and shows a dielectric constant equal or less than 8.

A method of manufacturing a TFT substrate includes the steps of forming an oxide semiconductor layer above a substrate, forming a first oxide film on the oxide semiconductor layer, performing oxidation processing on the oxide semiconductor layer after formation of the first oxide film, and forming a second oxide film on the first oxide film after the oxidation processing.

Provided herein are methods of depositing void-free cobalt into features with high aspect ratios. Methods involve (a) partially filling a feature with cobalt, (b) exposing the feature to a plasma generated from nitrogen-containing gas to selectively inhibit cobalt nucleation on surfaces near or at the top of the feature, optionally repeating (a) and (b), and depositing bulk cobalt into the feature by chemical vapor deposition. Methods may also involve exposing a feature including a barrier layer to a plasma generated from nitrogen-containing gas to selectively inhibit cobalt nucleation. The methods may be performed at low temperatures less than about 400° C. using cobalt-containing precursors. Methods may also involve using a remote plasma source to generate the nitrogen-based plasma. Methods also involve annealing the substrate.

A three-dimensional stacking structure and the manufacturing method(s) thereof are described. The stacking structure includes at least a bottom die, a top die and a spacer protective structure. The bottom die include contact pads in the non-bonding region. The top die is stacked on the bottom die without covering the contact pads of the bottom die and the bottom die is bonded with the top die through bonding structures there-between. The spacer protective structure is disposed on the bottom die and covers the top die to protect the top die. By forming an anti-bonding layer before stacking the top dies to the bottom dies, the top die can be partially removed to expose the contact pads of the bottom die for further connection.

Methods and systems for cyclic etching of a patterned layer are described. In an embodiment, a method includes receiving a substrate comprising an underlying layer, a mask layer that exposes portions of an intermediate layer that is disposed between the underlying layer and the mask layer. An embodiment may also include forming a first layer on the mask layer and a second layer on the exposed portions of the intermediate layer, the first layer and the second layer being concurrently formed. Additionally, the method may include removing, concurrently, the first layer and the second layer from the substrate. In such embodiments, the method may include alternating between the forming and the removing until portions of the underlying layer are exposed.

Aspects of the present disclosure include a method of forming a semiconductor interconnect structure and the interconnect structure. The method includes etching an opening in a first interconnect dielectric material. The method includes performing a nitridation process that converts the surfaces of the opening into nitride residues, and forms a nitrided interconnect dielectric material surface in the opening. The method includes depositing tantalum to create a tantalum layer on the nitrided interconnect dielectric surface region. The method includes depositing copper to fill the opening and planarizing the surface of the first dielectric material.

A method for fabricating a semiconductor device includes providing a substrate including a cell region and a core/peripheral region around the cell region, forming a gate insulating film on the substrate of the core/peripheral region, forming a first conductive film of a first conductive type on the gate insulating film, forming a diffusion blocking film within the first conductive film, the diffusion blocking film being spaced apart from the gate insulating film in a vertical direction, after forming the diffusion blocking film, forming an impurity pattern including impurities within the first conductive film, diffusing the impurities through a heat treatment process to form a second conductive film of a second conductive type and forming a metal gate electrode on the second conductive film, wherein the diffusion blocking film includes helium (He) and/or argon (Ar).