A method of forming a semiconductor device structure is provided. The method includes forming semiconductor fins at a first conductivity type region and a second conductivity type region of a substrate, forming a sacrificial gate structure across a portion of the semiconductor fins, wherein the sacrificial gate structure comprises a sacrificial gate dielectric layer and a sacrificial gate electrode layer over the sacrificial gate dielectric layer, and the sacrificial gate dielectric layer on the semiconductor fins of the first conductivity type region is asymmetrical in thickness between a top and a sidewall of the semiconductor fins. The method also includes forming a gate spacer on opposite sidewalls of the sacrificial gate structure, recessing the semiconductor fins not covered by the sacrificial gate structure and the gate spacer, forming source/drain feature on the recessed semiconductor fins, and removing the sacrificial gate structure to expose the top of the semiconductor fins.

A method for manufacturing a semiconductor device includes providing a substrate including a first device region and a second device region spaced apart from each other, forming a first oxide layer on the first device region and the second device region, forming a second oxide layer below the first oxide layer, forming a mask layer on the first oxide layer on the first device region while exposing the first oxide layer on the second device region, removing the first and second oxide layers on the second device region using the mask layer as a mask, removing the mask layer, and forming a gate oxide layer on the second device region. The thus formed gate oxide layer structure has improved quality and reliability.

A semiconductor device including an oxide-nitride-oxide (ONO) structure having a multi-layer charge storing layer and methods of forming the same are provided. Generally, the method involves: (i) forming a first oxide layer of the ONO structure; (ii) forming a multi-layer charge storing layer comprising nitride on a surface of the first oxide layer; and (iii) forming a second oxide layer of the ONO structure on a surface of the multi-layer charge storing layer. Preferably, the charge storing layer comprises at least two silicon oxynitride layers having differing stoichiometric compositions of Oxygen, Nitrogen and/or Silicon. More preferably, the ONO structure is part of a silicon-oxide-nitride-oxide-silicon (SONOS) structure and the semiconductor device is a SONOS memory transistor. Other embodiments are also disclosed.

The present disclosure provides a 1T1R resistive random access memory and a manufacturing method thereof, and a device. The 1T1R resistive random access memory includes: a memory cell array composed of multiple 1T1R resistive random access memory cells, each 1T1R resistive random access memory cell including a transistor and a resistance switching device (30). The transistor includes a channel layer (201), a gate layer (204) insulated from the channel layer (201), and a drain layer (203) and a source layer (202) disposed on the channel layer (201), and the drain layer (203) and the source layer (202) are vertically distributed on the channel layer (201). The resistance change device (30) is disposed near the drain layer (203). The disclosure reduces the area of a transistor, thereby significantly improving the memory density of the resistive random access memory.

Various embodiments of the present application are directed towards a semiconductor-on-insulator (SOI) substrate. The SOI substrate includes a handle substrate; a device layer overlying the handle substrate; and an insulator layer separating the handle substrate from the device layer. The insulator layer meets the device layer at a first interface and meets the handle substrate at a second interface. The insulator layer comprises a getter material having a getter concentration profile. The handle substrate contains getter material and has a handle getter concentration profile. The handle getter concentration profile has a peak at the second interface and a gradual decline beneath the second interface until reaching a handle getter concentration.

This disclosure relates to a method (100) for passivating a semiconductor structure, comprising a semiconductor layer and an oxide layer on the semiconductor layer; a semiconductor structure; and a vacuum processing system. The method (100) comprises providing the semiconductor structure (110) in a vacuum chamber (310) and, while keeping the semiconductor structure in the vacuum chamber (120) throughout a refinement period with a duration of at least 25 s refining the oxide layer (130) by maintaining temperature (131) of the semiconductor structure within a refinement temperature range extending from 20° C., to 800° C., and maintaining total pressure (132) in the vacuum chamber below a maximum total pressure, of 1×10.sup.−3 mbar.

Embodiments relate to a semiconductor structure and a method for fabricating the same. The method includes: providing a substrate, where a plurality of first trench initial structures are formed on the substrate, and the first trench initial structures extend along a first direction; and sequentially performing a thermal oxidation process and an oxide etching process on trench walls of the first trench initial structures to form first trenches whose trench widths satisfy a first preset dimension. The semiconductor structure and the method for fabricating the same can precisely control a trench width dimension of a trench, to form an isolation structure having a precise dimension in the trench, thereby effectively reducing parasitic capacitance and improving production yield and electrical properties of the semiconductor structure.

A substrate is patterned to form trenches and a semiconductor fin between the trenches. Insulators are formed in the trenches and a first dielectric layer is formed to cover the semiconductor fin and the insulators. A dummy gate strip is formed on the first dielectric layer. Spacers are formed on sidewalls of the dummy gate strip. The dummy gate strip and the first dielectric layer underneath are removed until sidewalls of the spacers, a portion of the semiconductor fin and portions of the insulators are exposed. A second dielectric layer is selectively formed to cover the exposed portion of the semiconductor fin, wherein a thickness of the first dielectric layer is smaller than a thickness of the second dielectric layer. A gate is formed between the spacers to cover the second dielectric layer, the sidewalls of the spacers and the exposed portions of the insulators.

A manufacturing method for a semiconductor structure includes: patterning and etching a semiconductor substrate to form a concave region; forming a first protective layer on a surface of the semiconductor substrate, the surface of the semiconductor substrate being a surface of a non-etched region except the concave region; forming an isolation structure in the concave region; and removing the first protective layer on the surface of the semiconductor substrate.

A method of forming an integrated circuit that includes placing a semiconductor substrate in a process chamber at an initial temperature, wherein one or more trenches are located within the semiconductor substrate. The temperature of the substrate is increased in a substantially oxygen-free ambient to an oxide-growth temperature. The temperature is then maintained at the oxide growth temperature while providing an oxidizing ambient, thereby forming an oxide layer on sidewalls of the trench. The temperature of the semiconductor wafer is then reduced to a final temperature below the initial temperature and removed from the process chamber.