An epitaxial growth process for a semiconductor device includes providing a semiconductor substrate, forming a plurality of Dummy Gate structures on the surface of the semiconductor substrate, and forming grooves in a self-aligned manner on both sides of the Dummy Gate structures; forming an initial seed layer on the inner side surfaces of the grooves, the thickness of the formed initial seed layer on the bottoms of the grooves being greater and the thickness of the formed initial seed layer on the sidewalls being smaller since the growth speed of crystal faces <100> and <110> is different; longitudinally etching the initial seed layer to thin the bottom of the initial seed layer to form a seed layer; forming a main body layer on the seed layer, the main body layer filling the grooves; and forming a cover layer on the main body layer.

The present disclosure describes a semiconductor structure and a method for forming the same. The method can include forming a recess structure in a substrate and forming a first semiconductor layer over the recess structure. The process of forming the first semiconductor layer can include doping first and second portions of the first semiconductor layer with a first n-type dopant having first and second doping concentrations, respectively. The second doping concentration can be greater than the first doping concentration. The method can further include forming a second semiconductor layer over the second portion of the first semiconductor layer. The process of forming the second semiconductor layer can include doping the second semiconductor layer with a second n-type dopant.

Gate-all-around integrated circuit structures having fin stack isolation, and methods of fabricating gate-all-around integrated circuit structures having fin stack isolation, are described. For example, an integrated circuit structure includes a sub-fin structure on a substrate, the sub-fin structure having a top and sidewalls. An isolation structure is on the top and along the sidewalls of the sub-fin structure. The isolation structure includes a first dielectric material surrounding regions of a second dielectric material. A vertical arrangement of horizontal nanowires is on a portion of the isolation structure on the top surface of the sub-fin structure.

A method of performing heteroepitaxy comprises exposing a substrate to a carrier gas, a first precursor gas, a Group II/III element, and a second precursor gas, to form a heteroepitaxial growth of one of GaAs, AlAs, InAs, GaP, InP, ZnSe, GaSe, CdSe, InSe, ZnTe, CdTe, GaTe, HgTe, GaSb, InSb, AlSb, CdS, GaN, and AlN on the substrate; wherein the substrate comprises one of GaAs, AlAs, InAs, GaP, InP, ZnSe, GaSe, CdSe, InSe, ZnTe, CdTe, GaTe, HgTe, GaSb, InSb, AlSb, CdS, GaN, and AlN; wherein the carrier gas is H.sub.2, wherein the first precursor is HCl, the Group II/III element comprises at least one of Zn, Cd, Hg, Al, Ga, and In; and wherein the second precursor is one of AsH.sub.3 (arsine), PH.sub.3 (phosphine), H.sub.2Se (hydrogen selenide), H.sub.2Te (hydrogen telluride), SbH.sub.3 (hydrogen antimonide), H.sub.2S (hydrogen sulfide), and NH.sub.3 (ammonia). The process may be an HVPE (hydride vapor phase epitaxy) process.

A boron nitride layer and a method of fabricating the same are provided. The boron nitride layer includes a boron nitride compound and has a dielectric constant of about 2.5 or less at an operating frequency of 100 kHz.

A semiconductor structure and a method of fabricating thereof is provided. The semiconductor structure may include a plurality of channel layers disposed over a semiconductor substrate, a plurality of metal gate (MGs) each disposed between two channel layers, an inner spacer disposed on a sidewall of each MG, a source/drain (S/D) feature disposed adjacent to the plurality of MGs, and a low-k dielectric feature disposed on the inner spacer, where the low-k dielectric feature extends into the S/D feature. The low-k dielectric feature may include two dissimilar dielectric layers, one of which may be air.

A method for method for manufacturing a rutile titanium dioxide layer according to the inventive concept includes forming a sacrificial layer on a substrate, and depositing a titanium dioxide (TiO.sub.2) material on the sacrificial layer. The sacrificial layer includes a metal oxide of a rutile phase. An amount of oxygen vacancy of the sacrificial layer after depositing the titanium dioxide material is greater than an amount of oxygen vacancy of the sacrificial layer before depositing the titanium dioxide material. The metal oxide includes a metal different from titanium (Ti).

A method includes forming a first semiconductor fin over a p-well region of a substrate; forming a second semiconductor fin over an n-well region of a substrate; forming a gate structure crossing the first semiconductor fin and the second semiconductor fin; performing an implantation process to form a source/drain doped region in the first semiconductor fin; etching the second semiconductor fin to form a recess therein; performing a first epitaxy process to grow a first epitaxy layer in the recess; performing a second epitaxy process to grow a second epitaxy layer over the first epitaxy process; etching the second epitaxy layer to round a corner of the second epitaxy layer; forming an interlayer dielectric (ILD) layer covering the first semiconductor fin and the second epitaxy layer, wherein no etching is performed to the first semiconductor fin after forming the gate structure and prior to forming the ILD layer.

The present disclosure describes epitaxial oxide high electron mobility transistors (HEMTs). In some embodiments, a HEMT comprises: a substrate; a first epitaxial semiconductor layer on the substrate; and a second epitaxial semiconductor layer on the first epitaxial semiconductor layer. The first epitaxial semiconductor layer can comprise a first oxide material, wherein the first oxide material can comprise a first polar material with an orthorhombic, tetragonal or trigonal crystal symmetry, and wherein the first oxide material can comprise a first conductivity type formed via polarization. The second epitaxial semiconductor layer can comprise a second oxide material.

A method includes providing a substrate having a first semiconductor material; creating a mask that covers an nFET region of the substrate; etching a pFET region of the substrate to form a trench; epitaxially growing a second semiconductor material in the trench, wherein the second semiconductor material is different from the first semiconductor material; and patterning the nFET region and the pFET region to produce a first fin in the nFET region and a second fin in the pFET region, wherein the first fin includes the first semiconductor material and the second fin includes a top portion over a bottom portion, wherein the top portion includes the second semiconductor material, and the bottom portion includes the first semiconductor material.