According to one embodiment, a semiconductor memory device includes a semiconductor substrate, a stacked body, a semiconductor member, a semiconductor portion, a first insulating film, and a charge storage film. The semiconductor member includes a first portion and a second portion, the first portion contacting with the semiconductor substrate, the second portion being provided on the first portion, contacting with the first portion, and having a second width smaller than a first width of the first portion in a first direction crossing a stacking direction. The first insulating film is provided on a side surface of the second portion. The charge storage film is provided on a side surface of the semiconductor portion, extends in the stacking direction, and includes a first portion located on an upper surface of the second portion of the semiconductor member.

There are provided methods of growing arrays of light emitters on substrates. An example method includes adjusting a growth parameter of a given light emitter of an array of light emitters on a substrate to obtain an adjusted growth parameter. The adjusting may be based on a location of the given light emitter on the substrate. The adjusting may be to compensate for nonuniformity in a growth profile of the light emitters across the substrate. The nonuniformity may be associated with a corresponding nonuniformity among wavelengths of light generated by the light emitters. Adjusting the growth parameter may be to adjust the corresponding nonuniformity. The method may also include growing the given light emitter on the substrate based on the adjusted growth parameter. Arrays of corresponding light emitters are also described.

A semiconductor rectifying device and a method of manufacturing the same. The semiconductor rectifying device includes: a substrate of a first conductivity type (100), an epitaxial layer of a first conductivity type (200) formed on the substrate of the first conductivity type (100), wherein the epitaxial layer of the first conductivity type (200) defines a plurality of trenches (310) thereon; a filling structure (300) comprising an insulating material formed on the inner surface of the trench (310) and a conductive material filled in the trench (310); a doped region of a second conductivity type (400) formed in the surface of the epitaxial layer of the first conductivity type (200) located between the filling structures (300); an upper electrode (600) formed on a surface of the epitaxial layer of the first conductivity type (200); a guard ring (700) formed in the surface layer of the epitaxial layer of the first conductivity type (200); and a guard layer (800).

The present disclosure discloses a semiconductor device with C-shaped channel portion, a method of manufacturing the same, and an electronic apparatus including the same. According to the embodiments, the semiconductor device may comprise a channel portion on a substrate, the channel portion including two or more curved nanosheets or nanowires spaced apart from each other in a lateral direction relative to the substrate and each having a C-shaped cross section; source/drain portions respectively located at upper and lower ends of the channel portion relative to the substrate; and a gate stack surrounding an outer circumference of each nanosheet or nanowire in the channel portion.

A method for producing a semiconductor chip (100) is provided, in which, during a growth process for growing a first semiconductor layer (1), an inhomogeneous lateral temperature distribution is created along at least one direction of extent of the growing first semiconductor layer (1), such that a lateral variation of a material composition of the first semiconductor layer (1) is produced. A semiconductor chip (100) is additionally provided.

A semiconductor substrate includes a base portion, an auxiliary layer and a surface layer. The auxiliary layer is formed on the base portion. The surface layer is formed on the auxiliary layer. The surface layer is in contact with a first main surface of the semiconductor substrate. The auxiliary layer has a different electrochemical dissolution efficiency than the base portion and the surface layer. At least a portion of the auxiliary layer and at least a portion of the surface layer are converted into a porous structure. Subsequently, an epitaxial layer is formed on the first main surface.

The present disclosure generally relates to process chambers for semiconductor processing. In one embodiment, a growth monitor for substrate processing is provided. The growth monitor includes a sensor holder and a crystal disposed in the sensor holder having a front side and a back side. An opening is formed in the sensor holder exposing a front side of the crystal. A gas inlet is disposed through the sensor holder to a plenum formed by the back side of the crystal and the sensor holder. A gas outlet is fluidly coupled to the plenum.

In one aspect, a method of fabricating a transistor includes depositing a first epitaxial layer, depositing a second epitaxial layer on the first epitaxial layer, implanting the second epitaxial layer to form a p-field termination region, depositing a third epitaxial layer on the p-field termination layer and forming trenches in the third epitaxial layer. The trenches include a trench gate of the transistor and a termination trench.

An apparatus is described. The apparatus includes a FINFET device having a channel. The channel is composed of a first semiconductor material that is epitaxially grown on a subfin structure beneath the channel. The subfin structure is composed of a second semiconductor material that is different than the first semiconductor material. The subfin structure is epitaxially grown on a substrate composed of a third semiconductor material that is different than the first and second semiconductor materials. The subfin structure has a doped region to substantially impede leakage currents between the channel and the substrate.

A method includes forming a first fin-group having has a plurality of semiconductor fins, and a second fin-group. The plurality of semiconductor fins include a first semiconductor fin, which is farthest from the second fin-group among the first fin-group, a second semiconductor fin, and a third semiconductor fin, which is closest to the second fin-group among the first fin-group. The method further includes performing an epitaxy process to form an epitaxy region based on the plurality of semiconductor fins. The epitaxy region includes a first portion and a second portion. The first portion is in middle between the first semiconductor fin and the second semiconductor fin. The first portion has a first top surface. The second portion is in middle between the second semiconductor fin and the third semiconductor fin. The second portion has a second top surface lower than the first top surface.