The invention is a special designed pattern heterogeneous substrate, which is epitaxially deposited on a heterogeneous substrate by two step growth, and a thermal cycle annealing is added to reduce the lattice mismatch between the layers and the difference in thermal expansion coefficient, thereby obtaining a better stress. The quality of the semiconductor epitaxial layer is improved, and the present invention can easily grasp the timing of stress release when the semiconductor is grown on the heterogeneous substrate, avoid cracks in the semiconductor epitaxial layer, and form a crack free zone in the middle of the semiconductor epitaxial layer.

The disclosure provides a method for passivating a silicon carbide epitaxial layer, relating to the technical field of semiconductors. The method includes the following steps: introducing a carbon source and a silicon source into a reaction chamber, and growing a silicon carbide epitaxial layer on a substrate; and turning off the carbon source, introducing a nitrogen source and a silicon source into the reaction chamber, and growing a silicon nitride thin film on an upper surface of the silicon carbide epitaxial layer. The silicon nitride thin film grown by the method has few defects and high quality, and may be used as a lower dielectric layer of a gate electrode in a field effect transistor. It does not additionally need an oxidation process to form a SiO.sub.2 dielectric layer, thereby reducing device fabrication procedures.

A method for manufacturing a transistor device includes a field oxide layer isolates an active region of a core device region from an active region of an input/output device region on a semiconductor substrate, the active region of the core device region is exposed by means of a mask layer, a gate-all-around structure is formed in the active region of the core device region, and a fin gate structure is formed in the active region of the input/output device region, thereby the on-current and off-current performance of the input/output device is not affected when the short channel effect of the core device is improved.

A superconductor tape and method for fabricating same are disclosed. Embodiments are directed to a superconductor tape including a substrate and a buffer stack. In one embodiment, the buffer stack includes: an Ion Beam-Assisted Deposition (IBAD) template layer above the substrate; a homo-epitaxial film of MgO or TiN above the IBAD template layer; an epitaxial film of silver above the homo-epitaxial film; and a homo-epitaxial film of LaMnO3 (LMO) above the silver epitaxial film. The superconductor tape also includes a superconductor film above the buffer stack. These and other embodiments achieve a LMO film with substantially improved texture, resulting in a superconductor structure having high critical current and significantly reduced power consumption and cost.

A method for fabricating a silicon carbide semiconductor device includes providing a SiC epitaxial layer disposed over a surface of a SiC substrate, forming an implant aperture in a hardmask layer on a surface of the expitaxial SiC layer, implanting contact and well regions in the SiC epitaxial layer through the hardmask layer, the contact region lying completely within and recessed from edges of the well region by performing one of implanting the well region through the implant aperture, reducing the area of the implant aperture forming a reduced-area contact implant aperture and implanting the contact region through the reduced-area implant aperture to form a contact region, and implanting the contact region through the implant aperture, increasing the area of the implant aperture to form a increased-area well implant aperture and implanting the well region through the increased-area implant aperture to form a well region completely surrounding the contact region.

Apparatus, systems, and methods for forming semiconductor materials (e.g., using nanofabrication) are generally described. In one example, a method comprises formation of a carbon buffer layer on a first substrate and a graphene layer on the carbon buffer layer by silicon sublimation, followed by removing the graphene layer so as to expose the carbon buffer layer and form a fabrication platform.

A semiconductor integrated circuit includes: a semiconductor base body of a first conductivity type; a first well region of a second conductivity type, deposited at an upper portion of the semiconductor base body, to which a first potential is applied; a second well region of the first conductivity type, deposited at an upper portion of the first well region, to which a second potential lower than the first potential is applied; a main electrode region to which the second potential is applied, the main electrode region being deposited at the upper portion of the first well region and away from the second well region; a first buried layer of the second conductivity type buried locally under the second well region; and a second buried layer of the second conductivity type buried locally under the main electrode region and away from the first buried layer.

The present disclosure provides methods for forming a metal containing material onto a substrate with good film uniformity and stress profile across the substrate. In one embodiment, a method of sputter depositing a metal containing layer on a substrate includes supplying a gas mixture into a processing chamber, forming a first portion of a metal containing layer on a substrate, transferring the substrate from the processing chamber, rotating the substrate, transferring the substrate back to the processing chamber, and forming a second portion of the metal containing layer on the first portion of the metal containing layer.

A method for manufacturing a gallium nitride semiconductor device includes: preparing a gallium nitride wafer; forming an epitaxial growth film on the gallium nitride wafer to provide a processed wafer having chip formation regions; perform a surface side process on a one surface side of the processed wafer; removing the gallium nitride wafer and dividing the processed wafer into a chip formation wafer and a recycle wafer; and forming an other surface side element component on an other surface side of the chip formation wafer.

The present invention provides standard wafers, a method of making the same and a calibration method. The method of making a standard wafer comprise providing a silicon substrate having a first conductive type; forming a reverse epitaxy layer having a second conductive type; forming a target epitaxy layer having the first conductive type; measuring a measurement of a resistivity of the target epitaxy layer with four point probing, the measurement being utilized as a standard resistivity of the standard wafer. In the present invention, the method of making a standard wafer is low-cost and convenient because the standard wafer is made with electrical isolation formed with the reverse epitaxy layer positioned between the silicon substrate and the target epitaxy layer formed after forming the reverse epitaxy layer facilitates in presenting a resistivity of the target epitaxy layer greater than 50 ohm/cm at first and then utilizing the four point probing to measure the resistivity of the target epitaxy layer as the resistivity of the standard wafer.