A method of forming a semiconductor structure includes performing a first deposition process to deposit a first high-K dielectric layer on a surface of a substrate, performing an interface formation process to form an interfacial layer on the surface of the substrate, performing a second deposition process to deposit a second high-K dielectric layer on the interfacial layer, performing a plasma nitridation process to insert nitrogen atoms in the first high-K dielectric layer and the second high-K dielectric layer, and performing an anneal process to passivate chemical bonds in the first high-K dielectric layer and the second high-K dielectric layer.

Apparatuses and methods for in-situ temperature measurement of a process chamber are described herein. A process chamber includes an infrared (IR) sensor mounted to the chamber wall. The IR sensor is mounted such that it can be oriented to receive an IR wave from targets within the process chamber through a view port in the chamber wall to detect a temperature of a surface inside the chamber, or to receive an IR wave from a target outside of the process chamber to detect an atmospheric temperature or a temperature of an exterior surface of the process chamber. As the orientation of the IR sensor is controllable to receive the IR wave from selected directions, it may be used to detect the temperature of various targets inside and outside the process chamber. The obtained temperature information is useful to improve overall chamber matching, processing throughput, and uniformity.

A method to integrate silicon-oxide-nitride-oxide-silicon (SONOS) transistors into a complementary metal-oxide-semiconductor (CMOS) flow including a triple gate oxide structure. The memory device may include a non-volatile memory (NVM) transistor that has a charge-trapping layer and a blocking dielectric, a first field-effect transistor (FET) including a first gate oxide of a first thickness, a second FET including a second gate oxide of a second thickness, a third FET including a third gate oxide of a third thickness, in which the first thickness is greater than the second thickness and the second thickness is greater than the third thickness.

A technique relates to in-situ cleaning of a high-mobility substrate. Alternating pulses of a metal precursor and exposure to a plasma of a gas or gas mixture are applied. The gas or gas mixture contains both nitrogen and hydrogen (e.g., NH.sub.3). A passivation layer is formed on the high-mobility substrate by alternating pulses of the metal precursor and exposure to the plasma of a gas, or gas mixture, containing both nitrogen and hydrogen.

A method for manufacturing a passivation stack on a crystalline silicon solar cell device. The method includes providing a substrate comprising a crystalline silicone layer such as a crystalline silicon wafer or chip, cleaning a surface of the crystalline silicon layer by removing an oxide layer at least from a portion of one side of the crystalline silicon layer, depositing, on at least a part of the cleaned surface, a layer of silicon oxynitride, and depositing a capping layer comprising a hydrogenated dielectric material on top of the layer of silicon oxynitride, wherein the layer of silicon oxynitride is deposited at a temperature from 100 C. to 200 C., and the step of depositing the layer of silicon oxynitride includes using N.sub.2O and SiH.sub.4 as precursor gasses in an N.sub.2 ambient atmosphere and depositing silicon oxynitride with a gas flow ratio of N.sub.2O to SiH.sub.4 below 2.

A method for in-situ dry cleaning of a SiGe semiconductor surface, ex-situ degreases the Ge containing semiconductor surface and removes organic contaminants. The surface is then dosed with HF (aq) or NH.sub.4F (g) generated via NH.sub.3+NH or NF.sub.3 with H.sub.2 or H.sub.2O to remove oxygen containing contaminants. In-situ dosing of the SiGe surface with atomic H removes carbon containing contaminants.

Techniques herein provide a chamber and substrate cleaning solution for etching and removing byproducts between separate etching steps. Such techniques include using a cleaning step based on fluorine chemistry, which is executed in between separate etch steps or divided etch steps. Such a technique can be executed in situ for improved efficiency. Other benefits include increasing etching depth/aspect ratios, and preventing post-etching defects including physical contact with neighboring gates, etc. Techniques herein are especially beneficial when applied to relatively small feature openings.

A semiconductor device includes: a semiconductor substrate; a gate electrode on the semiconductor substrate; a SiN film on the semiconductor substrate and the gate electrode; and an oxide film on the SiN film, wherein the oxide film is an atomic layer deposition film including atomic layers alternately deposited.

According to various embodiments, a method for processing a semiconductor layer may include: generating an etch plasma in a plasma chamber of a remote plasma source, wherein the plasma chamber of the remote plasma source is coupled to a processing chamber for processing the semiconductor layer; introducing the etch plasma into the processing chamber to remove a native oxide layer from a surface of the semiconductor layer and at most a negligible amount of semiconductor material of the semiconductor layer; and, subsequently, depositing a dielectric layer directly on the surface of the semiconductor layer.

A method of controlling the thickness of gate oxides in an integrated CMOS process which includes performing a two-step gate oxidation process to concurrently oxidize and therefore consume at least a first portion of the cap layer of the NV gate stack to form a blocking oxide and form a gate oxide of at least one metal-oxide-semiconductor (MOS) transistor in the second region, wherein the gate oxide of the at least one MOS transistor is formed during both a first oxidation step and a second oxidation step of the gate oxidation process.