A method for removing a native oxide film from a semiconductor substrate includes repetitively depositing layers of germanium on the native oxide and heating the substrate causing the layer of germanium to form germanium oxide, desorbing a portion of the native oxide film. The process is repeated until the oxide film is removed. A subsequent layer of strontium titanate can be deposited on the semiconductor substrate, over either residual germanium or a deposited germanium layer. The germanium can be converted to silicon germanium oxide by exposing the strontium titanate to oxygen.

A method for in-situ dry cleaning of a SiGe semiconductor surface doses the SiGe surface with ex-situ wet HF in a clean ambient environment or in-situ dosing with gaseous NH.sub.4F to remove oxygen containing contaminants. Dosing the SiGe surface with atomic H removes carbon containing contaminants. Low temperature annealing pulls the surface flat. Passivating the SiGe semiconductor surface with H.sub.2O.sub.2 vapor for a sufficient time and concentration forms an a oxygen monolayer(s) of —OH sites on the SiGe. Second annealing the SiGe semiconductor surface is conducted at a temperature below that which would induce dopant diffusion. A method for in-situ dry cleaning of a SiGe semiconductor surface, ex-situ degreases the Ge containing semiconductor surface and removes organic contaminants. The surface is then dosed with HF(aq) or NH4F(g) generated via NH.sub.3+NH or NF.sub.3 with H.sub.2 or H.sub.2O to remove oxygen containing contaminants. In-situ dosing of the SiGe surface with atomic H removes carbon containing contaminants.

A method and apparatus for depositing a material on a surface of a substrate are disclosed. The method can include a treatment step to suppress a rate of material deposition on the surface of the substrate. The method can result in higher-quality deposited material. Additionally or alternatively, the method can be used to fill a recess within the surface of the substrate with reduced or no seam formation.

There is included (a) loading a substrate where a conductive metal-element-containing film is exposed on a surface of the substrate into a process chamber under a first temperature; (b) supplying a reducing gas to the substrate while raising a temperature of the substrate to a second temperature higher than the first temperature in the process chamber; (c) forming a first film on the metal-element-containing film, by supplying a first process gas, which does not include an oxidizing gas, to the substrate under the second temperature in the process chamber; and (d) forming a second film on the first film such that the second film is thicker than the first film, by supplying a second process gas, which includes an oxidizing gas, to the substrate under a third temperature higher than the first temperature in the process chamber.

Provided are a chip matrix, a sequencing chip, and a manufacturing method thereof. The chip matrix includes: a wafer layer (111), the wafer layer (111) having cutting lines that are evenly distributed thereon; a first silicon oxide layer (112), the first silicon oxide layer (112) being made of silicon oxide and formed on an upper surface of the wafer layer (111); a transition metal oxide layer (113), the transition metal oxide layer (113) being made of transition metal oxide and formed on an upper surface of the first silicon oxide layer (112). The chip matrix has characteristics such as resistances against high temperature, high humidity and other harsh environments. Meanwhile, by changing pH, surfactant and other components of a solution containing sequences to be sequenced, a surface functional region of the chip matrix can specifically adsorb a sequence to be sequenced.

A method includes forming a first gate structure over a substrate, where the first gate structure is surrounded by a first dielectric layer; and forming a mask structure over the first gate structure and over the first dielectric layer, where forming the mask structure includes selectively forming a first capping layer over an upper surface of the first gate structure; and forming a second dielectric layer around the first capping layer. The method further includes forming a patterned dielectric layer over the mask structure, the patterned dielectric layer exposing a portion of the mask structure; removing the exposed portion of the mask structure and a portion of the first dielectric layer underlying the exposed portion of the mask structure, thereby forming a recess exposing a source/drain region adjacent to the first gate structure; and filling the recess with a conductive material.

Disclosed are apparatuses and methods for providing a substrate onto a substrate support in a processing chamber, generating an inert plasma in the processing chamber, and maintaining the inert plasma to heat the substrate to a steady state temperature, suitable for conducting plasma-enhanced chemical vapor deposition (PECVD), in less than 30 seconds from providing the substrate onto the substrate support. An apparatus may include a processing chamber, a process station that includes a substrate support, a process gas unit configured to flow an inert gas onto a substrate supported by the substrate support, a plasma source configured to generate an inert plasma in the process station, and a controller with instructions configured to flow the inert gas onto the substrate, generate the inert plasma in the first process station, and maintain the inert plasma to thereby heat the substrate.

Methods are provided for selective film deposition. One method includes providing a substrate containing a dielectric material and a metal layer, the metal layer having an oxidized metal layer thereon, coating the substrate with a metal-containing catalyst layer, treating the substrate with an alcohol solution that removes the oxidized metal layer from the metal layer along with the metal-containing catalyst layer on the oxidized metal layer, and exposing the substrate to a process gas containing a silanol gas for a time period that selectively deposits a SiO.sub.2 film on the metal-containing catalyst layer on the dielectric material.

There is provided a technique that includes: (a) forming a film formation suppression layer on a surface of a first material of a concave portion of the substrate, by supplying a precursor to the substrate provided with the concave portion on a surface of the substrate to adsorb at least a portion of a molecular structure of molecules constituting the precursor on the surface of the first material of the concave portion, the concave portion having a top surface and a side surface composed of the first material containing a first element and a bottom surface composed of a second material containing a second element; and (b) growing a film on a surface of the second material of the concave portion by supplying a film-forming material to the substrate having the film formation suppression layer formed on the surface of the first material.

A transistor and a method for fabricating the transistor are provided. The semiconductor structure transistor includes a base, a low-dimensional material layer, a plurality of spacers, a source, a drain, and a gate stack. The low-dimensional material layer is provided above the base. The plurality of spacers is provided on a surface of the low-dimensional material layer away from the base and spaced apart from each other. The source and the drain are provided on the surface of the low-dimensional material layer away from the base, respectively. The gate stack is provided on the surface of the low-dimensional material layer away from the base and between the source and the drain, in which the gate stack, the source and the drain are separated by the spacers, and in contact with the spacers, respectively. Therefore, the transistor has advantages of excellent comprehensive performance, high process compatibility, and good device uniformity.