A process for encapsulating an apparatus to restrict environmental element permeation between the apparatus and an external environment includes applying multiple barrier layers to the apparatus and preceding each layer application with a separate cleaning of the presently-exposed apparatus surface, resulting in an apparatus which includes an encapsulation stack, where the encapsulation stack includes a multi-layer stack of barrier layers. Each separate cleaning removes particles from the presently-exposed apparatus surface, exposing gaps in the barrier layer formed by the particles, and the subsequently-applied barrier layer at least partially fills the gaps, so that a permeation pathway through the encapsulation stack via gap spaces is restricted. The quantity of barrier layers applied to form the stack can be based on a determined probability that a stack of the particular quantity of barrier layers is independent of at least a certain quantity of continuous permeation pathways through the stack.

Atomic layer deposition processes for forming germanium oxide thin films are provided. In some embodiments the ALD processes can include the following: contacting the substrate with a vapor phase tetravalent Ge precursor such that at most a molecular monolayer of the Ge precursor is formed on the substrate surface; removing excess Ge precursor and reaction by products, if any; contacting the substrate with a vapor phase oxygen precursor that reacts with the Ge precursor on the substrate surface; removing excess oxygen precursor and any gaseous by-products, and repeating the contacting and removing steps until a germanium oxide thin film of the desired thickness has been formed.

Embodiments described herein provide a self-limiting and saturating SiO.sub.x bilayer process which does not require the use of a plasma or catalyst and that does not lead to undesirable substrate oxidation. Methods of the disclosure do not produce SiO.sub.2, but instead produce a saturated SiO.sub.x film with OH termination to make substrate surfaces highly reactive towards metal ALD precursors to seed high nucleation and growth of gate oxide ALD materials.

Methods of forming structures that include InP-based materials, such as a transistor operating as an inversion-type, enhancement-mode device are disclosed. A dielectric layer may be deposited by ALD over a semiconductor layer including In and P. A channel layer may be formed above a buffer layer having a lattice constant similar to a lattice constant of InP, the buffer layer being formed over a substrate having a lattice constant different from a lattice constant of InP.

There is provided a technique, which includes: (a) supplying a modifying agent to a substrate including a first surface and a second surface to form an inhibitor layer on the first surface and at least a portion of the second surface; and (b) forming a film on the second surface by performing a cycle a predetermined number of times, the cycle including (b1) supplying a precursor to the substrate and (b2) supplying a reactant to the substrate, wherein in (b), a process condition per cycle up to an n-th cycle is set to be different from a process condition per cycle on and after an (n+1)-th cycle, wherein n is an integer of 1 or 2 or more.

There is provided a technique that includes: (a) forming a film formation suppression layer on a surface of a first material of a concave portion of the substrate, by supplying a precursor to the substrate provided with the concave portion on a surface of the substrate to adsorb at least a portion of a molecular structure of molecules constituting the precursor on the surface of the first material of the concave portion, the concave portion having a top surface and a side surface composed of the first material containing a first element and a bottom surface composed of a second material containing a second element; and (b) growing a film on a surface of the second material of the concave portion by supplying a film-forming material to the substrate having the film formation suppression layer formed on the surface of the first material.

In some embodiments, the present disclosure relates to a method that includes forming a dielectric layer over a substrate and patterning the dielectric to form an opening in the dielectric layer. Further, a conductive material is formed within the opening of the dielectric layer. A planarization process is performed to remove portions of the conductive material arranged over the dielectric layer thereby forming a conductive feature within the opening of the dielectric layer. An anti-oxidation layer is formed on upper surfaces of the conductive feature, and then, the anti-oxidation layer is removed.

A substrate processing method includes providing a substrate containing a metal surface and a dielectric material surface, selectively forming a sacrificial capping layer containing a self-assembled monolayer on the metal surface, removing the sacrificial capping layer to restore the metal surface, and processing the restored metal surface and the dielectric material surface. The sacrificial capping layer may be used to prevent metal diffusion into the dielectric material and to prevent oxidation and contamination of the metal surface while waiting for further processing of the substrate.

A method includes forming a first gate structure over a substrate, where the first gate structure is surrounded by a first dielectric layer; and forming a mask structure over the first gate structure and over the first dielectric layer, where forming the mask structure includes selectively forming a first capping layer over an upper surface of the first gate structure; and forming a second dielectric layer around the first capping layer. The method further includes forming a patterned dielectric layer over the mask structure, the patterned dielectric layer exposing a portion of the mask structure; removing the exposed portion of the mask structure and a portion of the first dielectric layer underlying the exposed portion of the mask structure, thereby forming a recess exposing a source/drain region adjacent to the first gate structure; and filling the recess with a conductive material.

A method of reducing silicon consumption of a silicon material. The method comprises cleaning a silicon material and subjecting the cleaned silicon material to a vacuum anneal at a temperature below a melting point of silicon and under vacuum conditions. The silicon material is subjected to additional process acts without substantially removing silicon of the silicon material. Additional methods of forming a semiconductor structure and forming isolation structures are also disclosed.