Embodiments are directed to a method of passivating a surface of a high-mobility semiconductor and resulting structures having a reduced interface defect density. A semiconductor layer is formed on a substrate. A surface of the semiconductor layer is contacted with a sulfur source including thiourea at a temperature of up to about 90 degrees Celsius to form a sulfur passivation layer on the surface of the semiconductor layer. A dielectric layer is formed on the sulfur passivation layer and a minimum of interface trap density distribution at an interface between the semiconductor layer and the dielectric layer is less than about 2.010.sup.11 cm.sup.2 eV.sup.1.

Provided is a material composition and method for substrate modification. A substrate is patterned to include a plurality of features. The plurality of features includes a first subset of features having one or more substantially inert surfaces. In various embodiments, a priming material is deposited over the substrate, over the plurality of features, and over the one or more substantially inert surfaces. By way of example, the deposited priming material bonds at least to the one or more substantially inert surfaces. Additionally, the deposited priming material provides a modified substrate surface. After depositing the priming material, a layer is spin-coated over the modified substrate surface, where the spin-coated layer is substantially planar.

A method of forming an oxide layer includes the following steps. A substrate is provided. A surface of the substrate is treated to form an oxygen ion-rich surface. A spin-on-dielectric layer is formed on the oxygen ion-rich surface of the substrate. The present invention also provides a method of forming an oxide layer including the following steps. A substrate is provided. A surface of the substrate is treated with a hydrogen peroxide (H.sub.2O.sub.2) solution or a surface of the substrate is treated with oxygen containing gas, to form an oxygen ion-rich surface. A spin-on-dielectric layer is formed on the oxygen ion-rich surface of the substrate.

A method of manufacturing a metal compound film is a method of manufacturing a metal compound film in which a compound generating liquid containing, as a solute component, a substance that generates a metal compound is applied to a substrate having an opening portion on a surface and sintered to form a metal compound film, including: a pre-wet liquid application step of applying a pre-wet liquid to the surface of the substrate, and filling the opening portion with the pre-wet liquid, the pre-wet liquid having better wettability to the substrate than the compound generating liquid; a compound generating liquid application step of applying the compound generating liquid to stack the compound generating liquid on the pre-wet liquid on the substrate, and diffusing the solute component of the compound generating liquid in the pre-wet liquid; and a sintering step of sintering the applied compound generating liquid to form metal compound film.

A process for etching a substrate comprising polycrystalline silicon to form silicon nanostructures includes depositing metal on top of the substrate and contacting the metallized substrate with an etchant aqueous solution comprising about 2 to about 49 weight percent HF and an oxidizing agent.

Techniques herein provide methods for depositing spin-on metal materials for creating metal hard mask (MHM) structures without voids in the deposition. This includes effective spin-on deposition of TiOx, ZrOx, SnOx, HFOx, TaOx, et cetera. Such materials can help to provide differentiation of material etch resistivity for differentiation. By enabling spin-on metal hard mask (MHM) for use with a multi-line layer, a slit-based or self-aligned blocking strategy can be effectively used. Techniques herein include identifying a fill material to fill particular openings in a given relief pattern, modifying a surface energy value of surfaces within the opening such that a contact angle value of an interface between the fill material in liquid form and the sidewall or floor surfaces enables gap-free or void-free filling.

An array of elevationally-extending strings of memory cells comprises a vertical stack of alternating insulative levels and wordline levels. The wordline levels have terminal ends corresponding to control-gate regions. Charge-storage material of individual memory cells extend elevationally along individual of the control-gate regions of the wordline levels and do not extend elevationally along the insulative levels. A charge-blocking region of the individual memory cells extends elevationally along the individual control-gate regions of the wordline levels laterally through which charge migration between the individual control-gate regions and the charge-storage material is blocked. Channel material extends elevationally along the stack and is laterally spaced from the charge-storage material by insulative charge-passage material. All of the charge-storage material of individual of the elevationally-extending strings of memory cells is laterally outward of all of the insulative charge-passage material of the individual elevationally-extending strings of memory cells. Other embodiments, including method embodiments, are disclosed.

A solution deposition method includes: applying a liquid precursor solution to a substrate, the precursor solution including an oxide of a first metal, a hydroxide of the first metal, or a combination thereof, dissolved in an aqueous ammonia solution; evaporating the precursor solution to directly form a solid seed layer on the substrate, the seed layer including an oxide of the first metal, a hydroxide of the first metal, or a combination thereof, the seed layer being substantially free of organic compounds; and growing a bulk layer on the substrate, using the seed layer as a growth site or a nucleation site.

A process for encapsulating an apparatus to restrict environmental element permeation between the apparatus and an external environment includes applying multiple barrier layers to the apparatus and preceding each layer application with a separate cleaning of the presently-exposed apparatus surface, resulting in an apparatus which includes an encapsulation stack, where the encapsulation stack includes a multi-layer stack of barrier layers. Each separate cleaning removes particles from the presently-exposed apparatus surface, exposing gaps in the barrier layer formed by the particles, and the subsequently-applied barrier layer at least partially fills the gaps, so that a permeation pathway through the encapsulation stack via gap spaces is restricted. The quantity of barrier layers applied to form the stack can be based on a determined probability that a stack of the particular quantity of barrier layers is independent of at least a certain quantity of continuous permeation pathways through the stack.

A method for producing a low-defect interface between a GaN semiconductor substrate and a gate dielectric of a GaN power transistor. The method includes: introducing at least one GaN semiconductor substrate into a device; generating a vacuum within the device; heating the device to a first temperature; performing a first temperature step at the first temperature, wherein a reactive medium is introduced into the device and has a first partial pressure; performing a second temperature step at a second temperature, wherein an inert medium is introduced into the device and has a second partial pressure, and generating the gate dielectric on the GaN semiconductor substrate.