H01L21/02337

METAL RESISTORS HAVING NITRIDIZED DIELECTRIC SURFACE LAYERS AND NITRIDIZED METAL SURFACE LAYERS
20170301746 · 2017-10-19 ·

A semiconductor structure containing at least two metal resistor structures having different resistivities is provided and includes a first metal resistor structure located on a portion of a dielectric-containing substrate. The first metal resistor structure includes, from bottom to top, a first nitridized dielectric surface layer portion having a first nitrogen content, a first metal layer portion and a first nitridized metal surface layer. A second metal resistor structure is located on a second portion of the dielectric-containing substrate and spaced apart from the first metal resistor structure. The second metal resistor structure includes, from bottom to top, a second nitridized dielectric surface layer portion having a second nitrogen content, a second metal layer portion and a second nitridized metal surface layer. The second nitrogen content of the second nitridized dielectric surface layer portion differs from the first nitrogen content of the first nitridized dielectric surface layer portion.

Method of manufacturing semiconductor device and non-transitory computer-readable recording medium

To improve the characteristics of a film formed on a substrate, a method of manufacturing a semiconductor device includes: loading a substrate into a processing container, the substrate being provided with a film having a silazane bond, the film being subjected to pre-baking; supplying oxygen-containing gas at a first temperature not higher than the temperature of the pre-baking; and supplying processing gas containing at least any one of steam and hydrogen peroxide at a second temperature higher than the first temperature.

Interconnect integration for sidewall pore seal and via cleanliness

A method for sealing porous low-k dielectric films is provided. The method comprises exposing a substrate to UV radiation and a first reactive gas, wherein the substrate has an open feature defined therein, the open feature defined by a porous low-k dielectric layer and a conductive material, wherein the porous low-k dielectric layer is a silicon and carbon containing material and selectively forming a pore sealing layer in the open feature on exposed surfaces of the porous low-k dielectric layer using UV assisted photochemical vapor deposition.

Flowable CVD quality control in STI loop

A method for semiconductor processing includes forming a first dielectric layer comprising an N-type dopant over a first plurality of fins extending above a first region of a substrate, forming a second dielectric layer comprising a P-type dopant over the first plurality of fins and a second plurality of fins extending above a second region of the substrate, the second dielectric layer overlying the first dielectric layer, and forming an isolation layer between adjacent ones of the first plurality of fins, and between adjacent ones of the second plurality of fins. The method further includes performing an implantation process using a first dopant, the implantation process changing an etching rate of the isolation layer, and recessing the isolation layer, the first dielectric layer, and the second dielectric layer, where after the recessing, the first and the second plurality of fins extend above an upper surface of the isolation layer.

Method of removing oxide from substrate and method of manufacturing semiconductor device using the same

Provided is a method of removing native oxide from a substrate, the method including exposing the substrate to trimethyl aluminum (TMA) or dicyclopentadienyl magnesium (MgCp.sub.2) for a predetermined time.

Semiconductor Device and Method
20220052169 · 2022-02-17 ·

In an embodiment, a device includes: a gate structure over a substrate; a gate spacer adjacent the gate structure; a source/drain region adjacent the gate spacer; a first inter-layer dielectric (ILD) on the source/drain region, the first ILD having a first concentration of an impurity; and a second ILD on the first ILD, the second ILD having a second concentration of the impurity, the second concentration being less than the first concentration, top surfaces of the second ILD, the gate spacer, and the gate structure being coplanar; and a source/drain contact extending through the second ILD and the first ILD, the source/drain contact coupled to the source/drain region.

COMPOSITION FOR FORMING SILICA LAYER, METHOD FOR MANUFACTURING SILICA LAYER, AND SILICA LAYER

A composition for forming a silica layer, a method for manufacturing a silica layer, a silica layer manufactured by the method, and an electronic device including the silica layer. The composition for forming a silica layer includes a silicon-containing polymer and a solvent compound represented by Chemical Formula 1:

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METHOD FOR FABRICATING A FIN FIELD EFFECT TRANSISTOR AND A SHALLOW TRENCH ISOLATION

A method for fabricating a shallow trench isolation (STI) structure comprises the following steps. A silane-base precursor having a volumetric flowrate of 500 to 750 sccm and a nitrogen-base precursor having a volumetric flowrate of 300 to 600 sccm are introduced and mixed under a first pressure ranging from 0.5 to 1.5 torr at a first temperature ranging from 30 to 105 centigrade to deposit a flowable dielectric layer in a trench of a substrate. Then, ozone gas and oxygen gas are introduced and mixed under a second pressure ranging from 300 to 650 torr at a second temperature ranging from 50 to 250 centigrade to treat the flowable dielectric layer, wherein a volumetric flowrate ratio of ozone gas and oxygen gas ranges from 1:1 to 3:1. A method for fabricating a FinFET is provided.

Varying temperature anneal for film and structures formed thereby

Semiconductor device structures having dielectric features and methods of forming dielectric features are described herein. In some examples, the dielectric features are formed by an ALD process followed by a varying temperature anneal process. The dielectric features can have high density, low carbon concentration, and lower k-value. The dielectric features formed according to the present disclosure has improved resistance against etching chemistry, plasma damage, and physical bombardment in subsequent processes while maintaining a lower k-value for target capacitance efficiency.

INORGANIC POLYSILAZANE RESIN

An inorganic polysilazane resin of the present invention has a Si/N ratio (i.e. a ratio of contained silicon atoms to contained nitrogen atoms) of 1.30 or more. The inorganic polysilazane resin having such a high Si content can be produced by, for example, a method in which an inorganic polysilazane compound containing both Si—NH and Si—Cl is heated to react NH with Cl, a method in which a silazane oligomer (polymer) that leaves no Si—Cl bond is synthesized and a dihalosilane is added to the synthesized silazane oligomer (polymer) to perform a thermal reaction, and the like. A siliceous film can be formed by, for example, applying a coating composition containing the inorganic polysilazane resin onto a base plate and then dried and the dried product is then oxidized by bringing the dried product into contact with water vapor or hydrogen peroxide vapor and water vapor under heated conditions.