A substrate treating apparatus includes a front heat-treating block, a front relay block and a solution treating block. The front heat-treating block has heat-treating units and main transport mechanisms. The front relay block has receivers and transport mechanisms. The solution treating block has solution treating units and transport mechanisms for solution treatment. The front heat-treating block and front relay block are connected to be able to transport substrates reciprocally. The front relay block and solution treating block are connected to be able to transport the substrates reciprocally. The front relay block is disposed between the solution treating block and front heat-treating block.

In a preferred aspect, organic coating compositions, particularly antireflective coating compositions for use with an overcoated photoresist, are provided that comprise 1) one or more glycidyl groups; and 2) one or more aromatic groups that each comprises two or more substituents that comprise hydroxy, thiol and/or amine moieties. Catechol-containing polymers and methods for producing same also are provided.

Disclosed is a method of forming a semiconductor device. The method includes providing a precursor having a substrate and protrusions over the substrate. The protrusions are interposed by trenches. The method further includes depositing a first dielectric layer over the protrusions and filling the trenches. The first dielectric layer has a first hardness. The method further includes treating the first dielectric layer with an oxidizer. The method further includes performing a chemical mechanical planarization (CMP) process to the first dielectric layer.

Methods and devices for forming a conductive line disposed over a substrate. A first dielectric layer is disposed over the substrate and coplanar with the conductive line. A second dielectric layer disposed over the conductive line and a third dielectric layer disposed over the first dielectric layer. A via extends through the second dielectric layer and is coupled to the conductive line. The second dielectric layer and the third dielectric layer are coplanar and the second and third dielectric layers have a different composition. In some embodiments, the second dielectric layer is selectively deposited on the conductive line.

Embodiments described herein relate generally to methods for forming a conductive feature in a dielectric layer in semiconductor processing and structures formed thereby. In some embodiments, a structure includes a dielectric layer over a substrate, a surface modification layer, and a conductive feature. The dielectric layer has a sidewall. The surface modification layer is along the sidewall, and the surface modification layer includes phosphorous and carbon. The conductive feature is along the surface modification layer.

A method of forming a partially silicided element is provided. A silicided structure including a silicide layer on a base structure is formed. A dielectric region is formed over the silicided structure. The dielectric region is etched to form a contact opening exposing a first area of the silicide layer and a tub opening exposing a second area of the silicide layer. A conformal metal is deposited to (a) fill the contact opening to define a contact and (b) form a cup-shaped metal structure in the tub opening. Another etch is performed to remove the cup-shaped metal structure in the tub opening, to remove the underlying silicide layer second area and to expose an underlying area of the base structure, wherein the silicide layer first area remains intact. The base structure with the intact silicide layer first area and removed silicide layer second area defines the partially silicided element.

A method includes providing a first substrate having a first surface and a second substrate having a second surface, where the first surface and the second surface each include a silicon-based dielectric layer, applying hydrogen plasma to form hydrogen-terminated groups on the silicon-based dielectric layer, applying oxygen plasma to oxidize the silicon-based dielectric layer including the hydrogen-terminated groups, applying nitrogen plasma to the oxidized silicon-based dielectric layer, thereby forming a treated silicon-based dielectric layer, rinsing the treated silicon-based dielectric layer, and coupling the first substrate to the second substrate by physically contacting the rinsed and treated silicon-based dielectric layer on the first surface with the rinsed and treated silicon-based dielectric layer on the second surface.

A flash memory is provided and includes a substrate including a memory cell region; a memory transistor array including memory transistors and selecting transistors in the memory cell region; a functional layer covering outer surfaces of the memory transistors and selecting transistors, as well as surfaces of the substrate between adjacent memory transistors and selecting transistors; a dielectric layer covering top surfaces of the memory transistors and selecting transistors and fills gaps between each selecting transistor and a corresponding adjacent memory transistor; and air gaps formed between adjacent memory transistors. Each selecting transistor is used for selecting one column of memory transistors in the memory transistor array. The functional layer has a roughened surface capable of absorbing water. The air gaps in the flash memory are water vapor induced air gaps.

Provided is a composition for forming a film for semiconductor devices, including: a compound (A) including a SiO bond and a cationic functional group containing at least one of a primary nitrogen atom or a secondary nitrogen atom; a crosslinking agent (B) which includes three or more C(?O)OX groups (X is a hydrogen atom or an alkyl group having from 1 to 6 carbon atoms) in the molecule, in which from one to six of three or more C(?O)OX groups are C(?O)OH groups, and which has a weight average molecular weight of from 200 to 600; and a polar solvent (D).

In some embodiments, a flash memory and a fabricating method thereof are provided. The method includes proving a substrate including multiple memory transistors and selecting transistors; forming a functional layer covering outer surfaces of the memory transistors and selecting transistors, and surfaces of the substrate between adjacent memory transistors and selecting transistors; performing a surface roughening treatment to the functional layer to provide a roughed surface of the functional layer that absorbs water; and forming a dielectric layer using a chemical vapor deposition (CVD) process, the absorbed water is evaporated from the functional layer during the CVD process to form an upward air flow that resists the deposition of the dielectric layer, such that air gaps are formed between adjacent memory transistors, and the dielectric layer covers top surfaces of the plurality of memory transistors and selecting transistors and fills gaps between each selecting transistor and corresponding adjacent memory transistor.