A peeling method at low cost with high mass productivity is provided. An oxide layer is formed over a formation substrate, a first layer is formed over the oxide layer using a photosensitive material, an opening is formed in a portion of the first layer that overlaps with the oxide layer by a photolithography method and the first layer is heated to form a resin layer having an opening, a transistor including an oxide semiconductor in a channel formation region is formed over the resin layer, a conductive layer is formed to overlap with the opening of the resin layer and the oxide layer, the oxide layer is irradiated with light using a laser, and the transistor and the formation substrate are separated from each other.

A semiconductor device having favorable electrical characteristics is provided. A first oxide is formed over a substrate; a first insulator is formed over the first oxide; an opening reaching the first oxide is formed in the first insulator; a first oxide film is deposited in contact with the first oxide and the first insulator in the opening; a first insulating film is deposited over the first oxide film; microwave treatment is performed from above the first insulating film; heat treatment is performed on one or both of the first insulating film and the first oxide; a first conductive film is deposited over the first insulating film; and part of the first oxide film, part of the first insulating film, and part of the first conductive film are removed until a top surface of the first insulator is exposed, so that a second oxide, a second insulator, and a first conductor are formed. The microwave treatment is performed using a gas containing oxygen under reduced pressure, and the heat treatment is performed under reduced pressure.

An object of the present invention is to provide a technique suitable for achieving low wiring resistance and reducing a variation in the resistance value between semiconductor elements to be multilayered in a method of manufacturing a semiconductor device in which the semiconductor elements are multilayered through laminating semiconductor wafers via an adhesive layer. The method of the present invention includes first to third processes. In the first process, a wafer laminate Y is prepared, the wafer laminate Y having a laminated structure including a wafer 3, wafers 1T with a thickness from 1 to 20 um, and an adhesive layer 4 with a thickness from 0.5 to 4.5 μm interposed between a main surface 3a of the wafer 3 and a back surface 1b of the wafer 1T. In the second process, holes extending from the main surface 1a of the wafer 1T and reaching a wiring pattern of the wafer 3 are formed by a predetermined etching treatment. In the third process, the holes are filled with a conductive material to form through electrodes. The adhesive layer 4 has an etching rate of 1 to 2 μm/min in dry etching performed using an etching gas containing CF.sub.4, O.sub.2, and Ar at a volume ratio of 100:400:200 under predetermined conditions.

In one aspect, the invention is formulations comprising both organoaminohafnium and organoaminosilane precursor compounds that allows anchoring both silicon-containing fragments and hafnium-containing fragments onto a given surface having hydroxyl groups to deposit silicon doped hafnium oxide having a silicon doping level ranging from 0.5 to 8 mol %, suitable as ferroelectric material. In another aspect, the invention is methods and systems for depositing the silicon doped hafnium oxide films as ferroelectric materials using the formulations.

Techniques are disclosed for realizing a two-dimensional target lithography feature/pattern by decomposing (splitting) it into multiple unidirectional target features that, when aggregated, substantially (e.g., fully) represent the original target feature without leaving an unrepresented remainder (e.g., a whole-number quantity of unidirectional target features). The unidirectional target features may be arbitrarily grouped such that, within a grouping, all unidirectional target features share a common target width value. Where multiple such groupings are provided, individual groupings may or may not have the same common target width value. In some cases, a series of reticles is provided, each reticle having a mask pattern correlating to a grouping of unidirectional target features. Exposure of a photoresist material via the aggregated series of reticles substantially (e.g., fully) produces the original target feature/pattern. The pattern decomposition techniques may be integrated into any number of patterning processes, such as litho-freeze-litho-etch and litho-etch-litho-etch patterning processes.

An apparatus for thermal treatment of dielectric films on substrates includes: a microwave applicator cavity and microwave power source; a workpiece to be heated in the cavity, having a porous coating on a selected substrate; and, an apparatus for introducing a controlled amount of a polar species into the porous coating immediately before heating by the microwave power. The interaction of the polar species with the microwaves enhances the efficiency of the process, to shorten process time and reduce thermal budget. A related method includes: depositing a porous film on a substrate; soft baking the film to a selected state of dryness; introducing a controlled amount of a polar species into the soft baked film; and, applying microwave energy to heat the film via interaction with the polar species.

Disclosed herein are techniques for providing isolation in integrated circuit (IC) devices, as well as IC devices and computing systems that utilize such techniques. In some embodiments, a protective layer may be disposed on a structure in an IC device, prior to deposition of additional dielectric material, and the resulting assembly may be treated to form a dielectric layer around the structure.

A fabrication method of a semiconductor device comprises the steps of: providing a substrate, which is divided into several chip areas; forming a protective layer on the substrate, the protective layer covers the scribe lines and the chip areas; exposing and developing the protective layer to form a plurality of grooves in the protective layer over the chip areas, and the depth of the grooves is smaller than the initial thickness of the protective layer.

An imprint apparatus cures an imprint material on a shot region of a substrate by light irradiation and forms a pattern on the shot region in a state in which a mold is in contact with the imprint material. The apparatus includes a shutter mechanism including a shutter plate configured to control light irradiation to the imprint material on the shot region and an actuator configured to drive the shutter plate, and a driving mechanism configured to change relative positions of the substrate and the mold. The shutter plate includes a first passing portion configured to irradiate a part out of a whole of the imprint material on the shot region with light and a second passing portion configured to irradiate the whole of the imprint material on the shot region.

Integrated circuitry comprises an electronic component. Insulative silicon dioxide is adjacent the electronic component. The insulative silicon dioxide has at least one of (a) and (b), where: (a): an average concentration of elemental-form H of 0.002 to 0.5 atomic percent; and (b): an average concentration of elemental-form N of 0.005 to 0.3 atomic percent. Other embodiments, including method, are disclosed.