The present disclosure pertains to embodiments of a semiconductor processing system and method for treating a semiconductor wafer. The processing system comprises a reactor, a wafer handling assembly, and treatment unit disposed vertically adjacent to the wafer handling assembly. The system and method minimize a total floor space occupied by the system without sacrificing the processing capacity.

Exemplary methods of semiconductor processing may include providing a silicon-containing precursor to a processing region of a semiconductor processing chamber. A substrate may be disposed within the processing region of the semiconductor processing chamber. The substrate may define one or more features along the substrate. The methods may include depositing a silicon-containing material on the substrate. The silicon-containing material may extend within the one or more features along the substrate. The methods may include providing an oxygen-containing precursor. The methods may include annealing the silicon-containing material with the oxygen-containing precursor. The annealing may cause the silicon-containing material to expand within the one or more features. The methods may include repeating one or more of the operations to iteratively fill the one or more features on the substrate.

Embodiment methods for performing a high pressure anneal process during the formation of a semiconductor device, and embodiment devices therefor, are provided. The high pressure anneal process may be a dry high pressure anneal process in which a pressurized environment of the anneal includes one or more process gases. The high pressure anneal process may be a wet anneal process in which a pressurized environment of the anneal includes steam.

A semiconductor device of an embodiment is manufactured by forming a first layer by applying a liquid containing silicon oxide particles onto a first substrate, performing a first heat treatment, forming a second layer including a first insulator on the upper surface and the side surfaces of the first layer, forming a third layer including an electronic circuit on the second layer, bonding a second substrate including a semiconductor circuit to the third layer, and separating the first substrate and the second substrate at the first layer.

Methods of manufacturing memory devices are provided. The methods improve the quality of a selectively deposited silicon-containing dielectric layer. The method comprises selectively depositing a silicon-containing dielectric layer in a recessed region of a film stack. The selectively deposited silicon-containing dielectric layer is then exposed to a high-density plasma and annealed at a temperature greater than 800 ° C. to provide a silicon-containing dielectric film having a wet etch rate of less than 4 Å/min.

Integrated circuitry comprises an electronic component. Insulative silicon dioxide is adjacent the electronic component. The insulative silicon dioxide has at least one of (a) and (b), where: (a): an average concentration of elemental-form H of 0.002 to 0.5 atomic percent; and (b): an average concentration of elemental-form N of 0.005 to 0.3 atomic percent. Other embodiments, including method, are disclosed.

A semiconductor device of an embodiment is manufactured by forming a first layer by applying a liquid containing silicon oxide particles onto a first substrate, performing a first heat treatment, forming a second layer including a first insulator on the upper surface and the side surfaces of the first layer, forming a third layer including an electronic circuit on the second layer, bonding a second substrate including a semiconductor circuit to the third layer, and separating the first substrate and the second substrate at the first layer.

Disclosed herein are techniques for providing isolation in integrated circuit (IC) devices, as well as IC devices and computing systems that utilize such techniques. In some embodiments, a protective layer may be disposed on a structure in an IC device, prior to deposition of additional dielectric material, and the resulting assembly may be treated to form a dielectric layer around the structure.

Integrated circuitry comprises an electronic component. Insulative silicon dioxide is adjacent the electronic component. The insulative silicon dioxide has at least one of (a) and (b), where: (a): an average concentration of elemental-form H of 0.002 to 0.5 atomic percent; and (b): an average concentration of elemental-form N of 0.005 to 0.3 atomic percent. Other embodiments, including method, are disclosed.

A method of forming a semiconductor structure, the method comprises: providing a non-planar surface in the manufacturing of a silicon carbide (SiC) device; depositing a reflowable dielectric material on said non-planar surface; and heating said reflowable dielectric material to a temperature and for a time sufficient to cause reflowing of said reflowable dielectric material and thereby provide a dielectric layer comprising a substantially planar surface, wherein said dielectric layer is substantially free of voids.