A method of forming crystallographically stabilized ferroelectric hafnium zirconium based films for semiconductor devices is described. The hafnium zirconium based films can be either doped or undoped. The method includes depositing a hafnium zirconium based film with a thickness greater than 5 nanometers on a substrate, depositing a cap layer on the hafnium zirconium based film, heat-treating the substrate to crystallize the hafnium zirconium based film in a non-centrosymmetric orthorhombic phase, a tetragonal phase, or a mixture thereof. The method further includes removing the cap layer from the substrate, thinning the heat-treated hafnium zirconium based film to a thickness of less than 5 nanometers, where the thinned heat-treated hafnium zirconium based film maintains the crystallized non-centrosymmetric orthorhombic phase, the tetragonal phase, or the mixture thereof.

A method of forming an electrical contact in a semiconductor structure includes performing a patterning process to form a hard mask on a semiconductor structure comprising a first semiconductor region, a second semiconductor region, a dielectric layer having a first opening over the first semiconductor region and a second opening over the second semiconductor region, wherein the hard mask covers an exposed surface of the first semiconductor region within the first opening, performing a first selective deposition process to form a contact layer on the exposed surface of the second semiconductor region within the second opening, and performing a second selective deposition process to form a cap layer on the contact layer.

The present disclosure involves forming a porous low-k dielectric structure. A plurality of conductive elements is formed over the substrate. The conductive elements are separated from one another by a plurality of openings. A barrier layer is formed over the conductive elements. The barrier layer is formed to cover sidewalls of the openings. A treatment process is performed to the barrier layer. The barrier layer becomes hydrophilic after the treatment process is performed. A dielectric material is formed over the barrier layer after the treatment process has been performed. The dielectric material fills the openings and contains a plurality of porogens.

Methods and devices for forming a conductive line disposed over a substrate. A first dielectric layer is disposed over the substrate and coplanar with the conductive line. A second dielectric layer disposed over the conductive line and a third dielectric layer disposed over the first dielectric layer. A via extends through the second dielectric layer and is coupled to the conductive line. The second dielectric layer and the third dielectric layer are coplanar and the second and third dielectric layers have a different composition. In some embodiments, the second dielectric layer is selectively deposited on the conductive line.

Embodiments disclosed herein relate generally to capping processes and structures formed thereby. In an embodiment, a conductive feature, formed in a dielectric layer, has a metallic surface, and the dielectric layer has a dielectric surface. The dielectric surface is modified to be hydrophobic by performing a surface modification treatment. After modifying the dielectric surface, a capping layer is formed on the metallic surface by performing a selective deposition process. In another embodiment, a surface of a gate structure is exposed through a dielectric layer. A capping layer is formed on the surface of the gate structure by performing a selective deposition process.

The present invention relates to new aromatic-amino functional siloxanes, which are compounds comprising one or two tail groups X.sub.2, and a linking group L of structure (2) linking each said tail group to said head group, wherein the head group X has structure (1), containing an optional organic moiety Y, wherein the attachment point of said tail group X.sub.2 through said linking group L to the head group X.sub.1, may be, at positions a, b, c, d, or e. Another aspect of this invention are compositions containing these novel aromatic amino functional siloxane. A further aspect of this invention are compositions comprised of the above novel aromatic-amino functional siloxanes, and also the composition resulting from the aging of these compositions at room temperature for about 1 day to about 4 weeks. Still further aspects of this invention are processes for forming self-assembled monolayers on a substrate, from the aged composition, and also the processes of coating these aged compositions on patterned porous dielectrics to cap them also the processes of metallization of these capped pattered porous dielectrics.

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A semiconductor structure includes a high-k metal gate structure (HKMG) disposed over a channel region of a semiconductor layer formed over a substrate, where the HKMG includes an interfacial layer disposed over the semiconductor layer, a high-k dielectric layer disposed over the interfacial layer, and a gate electrode disposed over the high-k dielectric layer, where a length of the high-k dielectric layer is greater than a length of the gate electrode and where outer edges of the interfacial layer, the high-k dielectric layer, and the gate electrode form a step profile. The semiconductor structure further includes gate spacers having sidewall portions contacting sidewalls of the gate electrode and bottom portions contacting top portions of the high-k dielectric layer and the interfacial layer, and source/drain features disposed in the semiconductor layer adjacent to the HKMG.

A method of fabricating a semiconductor package includes providing a substrate on a stage, the substrate including semiconductor dies and a modified layer along a partition lane and sequentially having an adhesive film and a base film on a surface thereof so that bottom surfaces of the adhesive film and the base film face the stage and top surfaces of the adhesive film and the base film face away from the stage and the bottom surface of the adhesive film faces the top surface of the base film; separating the semiconductor dies from each other by applying a force to the substrate in a lateral direction; applying a gas pressure to a top surface of each of the semiconductor dies; and irradiating ultraviolet rays toward the adhesive film after applying the gas pressure on the top surface of each of the semiconductor dies.

Certain aspects of the present disclosure generally relate to a high electron mobility transistor and techniques for fabricating the same. Certain aspects of the present disclosure are directed to a semiconductor device. The semiconductor device generally includes a substrate; a channel region having a fin disposed above the substrate; a first barrier layer disposed adjacent to a first side and a second side of the first fin, wherein the first side and the second side of the first fin are opposite sides, the first barrier layer forming a heterojunction with the fin; a first dielectric layer disposed adjacent to a first side and a second side of the first barrier layer, wherein the first side and the second side of the first barrier layer are opposite sides; and a first gate region disposed adjacent to the first dielectric layer.

A method of fabricating a metallization layer of a semiconductor device in which one or more interconnect structures are to be formed includes depositing a dielectric layer and forming a trench for each interconnect structure to be formed in the metallization layer. An insulating liner layer is deposited that serves both as a metal diffusion barrier and as a metal adhesion layer for the interconnect structures.