Methods of forming SOI substrates are disclosed. In some embodiments, an epitaxial layer and an oxide layer are formed on a sacrificial substrate. An etch stop layer is formed in the epitaxial layer. The sacrificial substrate is bonded to a handle substrate at the oxide layer. The sacrificial substrate is removed. The epitaxial layer is partially removed until the etch stop layer is exposed.

Information about a process for depositing at least one layer on a substrate in a process chamber is obtained via a method including the step of storing actuation data and sensor values as raw data in a log file, together with their time reference. Knowledge about the quality of the deposited layer is obtained by using the raw data. For this purpose, process parameters are obtained from the raw data by means of a computing apparatus. The beginning and the end of the process steps for processing the substrate and their respective types are identified by analyzing the time curve of the process parameters. For at least some of the process steps, characteristic process step quantities corresponding to the particular type of the process steps are calculated from the measured values, and the obtained process step quantities are compared with comparison quantities associated with one or more similar process steps.

Provided is a semiconductor device including graphene. The semiconductor device includes: a substrate including an insulator and a semiconductor; and a graphene layer configured to directly grow only on a surface of the semiconductor, wherein the semiconductor includes at least one of a group IV material and a group III-V compound.

An upper layer (4,5) made of non-doped III-V compound semiconductor is formed on a lower layer (3) made of non-doped III-V compound semiconductor. Impurity source gas is fed through vapor phase diffusion using an organometallic vapor-phase epitaxy device to add an impurity to the upper layer (4,5). The vapor phase diffusion is continued with the feed of the impurity source gas stopped or with a feed amount of the impurity source gas lowered.

A nanowire structure includes a substrate, a graded planar buffer layer, a patterned mask, and a nanowire. The graded planar buffer layer is on the substrate. The patterned mask is on the graded planar buffer layer and includes an opening through which the graded planar buffer layer is exposed. The nanowire is on the graded planar buffer layer in the opening of the patterned mask. A lattice constant of the graded planar buffer layer is between a lattice constant of the substrate and a lattice constant of the nanowire. By providing the graded planar buffer layer, lattice mismatch between the nanowire and the substrate can be reduced or eliminated, thereby improving the quality and performance of the nanowire structure.

A method for printing a semiconductor material includes depositing a molten metal onto a substrate in an enclosed chamber to form a trace having a maximum height of 15 micrometers, a maximum width of 25 micrometers to 10 millimeters, and/or a thin film having a maximum height of 15 micrometers. The method further includes reacting the molten metal with a gas phase species in the enclosed chamber to form the semiconductor material.

An intermediate structure for forming a semiconductor device and method of making is provided. The intermediate device includes (i) a substrate comprising a Ga-based layer, and (ii) optionally, a metal layer on the substrate; wherein at least one of the Ga-based layer and, if present, the metal layer comprises at least a surface region having an isoelectric point of less than 7, usually at most 6.

Methods of forming SOI substrates are disclosed. In some embodiments, an epitaxial layer and an oxide layer are formed on a sacrificial substrate. An etch stop layer is formed in the epitaxial layer. The sacrificial substrate is bonded to a handle substrate at the oxide layer. The sacrificial substrate is removed. The epitaxial layer is partially removed until the etch stop layer is exposed.

A method for fabricating a semiconductor substrate comprises providing a crystalline base substrate, forming an insulating layer on the crystalline base substrate and forming a trench in the insulating layer. This exposes a seed surface of the base substrate. The trench has sidewalls and a bottom. The bottom corresponds to the seed surface of the base substrate. The method further comprises growing, at a first growth step, an elongated seed structure in the trench from the seed surface of the substrate and forming a cavity structure above the insulating layer. The cavity structure covers the elongated seed structure and extends laterally to the elongated seed structure. The method comprises a further step of growing, at a second growth step, the semiconductor substrate in the cavity structure from the elongated seed structure. The invention is notably also directed to corresponding semiconductor structures and corresponding semiconductor substrates.

An upper layer (4,5) made of non-doped III-V compound semiconductor is formed on a lower layer (3) made of non-doped III-V compound semiconductor. Impurity source gas is fed through vapor phase diffusion using an organometallic vapor-phase epitaxy device to add an impurity to the upper layer (4,5). The vapor phase diffusion is continued with the feed of the impurity source gas stopped or with a feed amount of the impurity source gas lowered.