Semiconductor structures and methods for forming those semiconductor structures are disclosed. For example, a semiconductor structure with a p-type superlattice region, an i-type superlattice region, and an n-type superlattice region is disclosed. The semiconductor structure can have a polar crystal structure with a growth axis that is substantially parallel to a spontaneous polarization axis of the polar crystal structure. In some cases, there are no abrupt changes in polarisation at interfaces between each region. At least one of the p-type superlattice region, the i-type superlattice region and the n-type superlattice region can comprise a plurality of unit cells exhibiting a monotonic change in composition from a wider band gap (WBG) material to a narrower band gap (NBG) material or from a NBG material to a WBG material along the growth axis to induce p-type or n-type conductivity.

A lattice matched epitaxial oxide interlayer is disposed between each semiconductor layer of a graded buffer layer material stack. Each lattice matched epitaxial oxide interlayer inhibits propagation of threading dislocations from one semiconductor layer of the graded buffer layer material stack into an overlying semiconductor layer of the graded buffer layer material stack. This allows for decreasing the thickness of each semiconductor layer within the graded buffer layer material stack. The topmost semiconductor layer of the graded buffer layer material stack, which is a relaxed layer, contains a lower defect density than the other semiconductor layers of the graded buffer layer material stack.

Disclosed is a method of manufacturing a gallium oxide thin film for a power semiconductor using a dopant activation technology that maximizes dopant activation effect and rearrangement effect of lattice in a grown epitaxial at the same time by performing in-situ annealing in a growth condition of a nitrogen atmosphere at the same time as the growth of a doped layer is finished.

A semiconductor element includes a high-resistivity substrate that includes a β-Ga.sub.2O.sub.3-based single crystal including an acceptor impurity, a buffer layer on the high-resistivity substrate, the buffer layer including a β-Ga.sub.2O.sub.3-based single crystal, and a channel layer on the buffer layer, the channel layer including a β-Ga.sub.2O.sub.3-based single crystal including a donor impurity. A crystalline laminate structure includes a high-resistivity substrate that includes a β-Ga.sub.2O.sub.3-based single crystal including an acceptor impurity, a buffer layer on the high-resistivity substrate, the buffer layer including a β-Ga.sub.2O.sub.3-based single crystal, and a donor impurity-containing layer on the buffer layer, the donor impurity-containing layer including a β-Ga.sub.2O.sub.3-based single crystal including a donor impurity.

A multilayer structure including a hexagonal epitaxial layer, such as GaN or other group III-nitride (III-N) semiconductors, a <111> oriented textured layer, and a non-single crystal substrate, and methods for making the same. The textured layer has a crystalline alignment preferably formed by the ion-beam assisted deposition (IBAD) texturing process and can be biaxially aligned. The in-plane crystalline texture of the textured layer is sufficiently low to allow growth of high quality hexagonal material, but can still be significantly greater than the required in-plane crystalline texture of the hexagonal material. The IBAD process enables low-cost, large-area, flexible metal foil substrates to be used as potential alternatives to single-crystal sapphire and silicon for manufacture of electronic devices, enabling scaled-up roll-to-roll, sheet-to-sheet, or similar fabrication processes to be used. The user is able to choose a substrate for its mechanical and thermal properties, such as how well its coefficient of thermal expansion matches that of the hexagonal epitaxial layer, while choosing a textured layer that more closely lattice matches that layer.

Systems and methods for forming semiconductor layers, including oxide-based layers, are disclosed in which a material deposition system has a rotation mechanism that rotates a substrate around a center axis of the substrate. The system includes a heater configured to heat the substrate and a positioning mechanism that allows dynamic adjusting of an orthogonal distance, a lateral distance, and a tilt angle of an exit aperture of a material source relative to the substrate. In some embodiments, the dynamic adjusting is based on a desired layer uniformity for a desired layer growth rate. In some embodiments, the orthogonal distance, the lateral distance, or the tilt angle depends on a predetermined material ejection spatial distribution of the material source.

In some embodiments, an optoelectronic semiconductor light emitting device includes: a substrate; and a plurality of epitaxial semiconductor layers disposed on the substrate. Each of the epitaxial semiconductor layers can comprise an epitaxial oxide. At least one of the epitaxial semiconductor layers can comprise an optically emissive material of direct bandgap type. At least one of the epitaxial semiconductor layers can comprise (Al.sub.x1Ga.sub.1−x1).sub.2O.sub.3 wherein 0≤x1≤1. The plurality of epitaxial semiconductor layers can comprise: first region comprising a first conductivity type; a second region comprising a not-intentionally doped (NID) intrinsic region; and a third region comprising a second conductivity type. The substrate and the plurality of epitaxial semiconductor layers can be a substantially single crystal epitaxially formed device. The optoelectronic semiconductor light emitting device can be configured to emit light having a wavelength in a range from 150 nm to 425 nm.

An amount of nitrogen in a compound film is controlled. A method of manufacturing compound film comprising forming films laminated on a substrate placed at a film forming chamber is provided. According to the method of manufacturing compound film, a first compound layer including one or more elements selected from metal elements and semimetal elements and oxygen element and a second compound layer including one or more elements and nitrogen element are laminated alternately. The first compound layer is formed by a Filtered Arc Ion Plating method and the second compound layer is formed by a sputtering method.

A thin film transistor and a manufacturing method thereof, a display substrate and a display device are provided. The method of manufacturing the thin film transistor comprises forming an active layer (4) having characteristics of crystal orientation of C-axis on a substrate (1) by using indium gallium zinc oxide (InGaO.sub.3(ZnO).sub.m), where m≧2. The active layer fabricated with InGaO.sub.3(ZnO).sub.m has a good electron mobility, and the quality of the fabricated active layer is improved.

An Oxide TFT, a preparation method thereof, an array substrate and a display device are described. The method includes forming a gate electrode, a gate insulating layer, a channel layer, a barrier layer, as well as a source electrode and a drain electrode on a substrate; the channel layer is formed by depositing an amorphous oxide semiconductor film in a first mixed gas containing H.sub.2, Ar and O.sub.2. By depositing a channel layer in a first mixed gas containing H.sub.2, Ar and O.sub.2, the hysteresis phenomenon of the TFT can be mitigated effectively to improve the display quality of the display panel.