An integrated circuit structure includes a first transistor, an interconnect structure, a first dielectric layer, polycrystalline plugs, a semiconductor structure and a second transistor. The first transistor is formed on a substrate. The interconnect structure is over the first transistor. The first dielectric layer is over the interconnect structure. The polycrystalline plugs extend from a top surface of the dielectric layer into the dielectric layer. The semiconductor structure is disposed over the first dielectric layer. The second transistor is formed on the semiconductor structure.

A layered structure comprising a substrate having a first deformation. Also one or more device layers forming a device and having a second deformation. A deformation control layer which is pseudomorphic with respect to the substrate and having a third deformation. The deformation control layer is selected such that a sum of the first, second and third deformations matches a target level of deformation. Advantageously the layered structure has a controlled, known deformation which can be compressive, tensile or zero.

A method includes following steps. An interconnect structure is formed over a first transistor. A dielectric layer is formed over the interconnect structure. The dielectric layer is etched to form holes in the dielectric layer. An amorphous layer is deposited in the holes of the dielectric layer and on a top surface of the dielectric layer. The amorphous layer is crystallized into a polycrystalline layer. A second transistor is formed on the polycrystalline layer.

In a semiconductor manufacturing method, a mask is disposed on a semiconductor layer or semiconductor substrate. The semiconductor layer or semiconductor substrate is etched in an area delineated by the mask to form a cavity. With the mask disposed on the semiconductor layer or semiconductor substrate, the cavity is lined to form a containment structure. With the mask disposed on the semiconductor layer or semiconductor substrate, the containment structure is filled with a base semiconductor material. After filling the containment structure with the base semiconductor material, the mask is removed. At least one semiconductor device is fabricated in and/or on the base semiconductor material deposited in the containment structure.

Described herein are systems and methods of utilizing nanochannels generated in the sacrificial layer of a semiconductor substrate to increase epitaxial lift-off speeds and facilitate reusability of GaAs substrates. The provided systems and methods may utilize unique nanochannel geometries to increase the surface area exposed to the etchant and further decrease etch times.

A method for manufacturing a vertical JFET includes providing a III-nitride substrate having a first conductivity type; forming a first III-nitride layer coupled to the III-nitride substrate, wherein the first III-nitride layer is characterized by a first dopant concentration and the first conductivity type; forming a plurality of trenches within the first III-nitride layer, wherein the plurality of trenches extend to a predetermined depth; epitaxially regrowing a second III-nitride structure in the trenches, wherein the second III-nitride structure is characterized by a second conductivity type; forming a plurality of III-nitride fins, each coupled to the first III-nitride layer, wherein the plurality of III-nitride fins are separated by one of a plurality of recess regions; epitaxially regrowing a III-nitride gate layer in the recess regions, wherein the III-nitride gate layer is coupled to the second III-nitride structure, and wherein the III-nitride gate layer is characterized by the second conductivity type.

A method for semiconductor film lift-off and substrate transfer is provided. It includes: preparing a semiconductor film-substrate structure including a first substrate layer, multiple seed crystal structures and a semiconductor film layer stacked in that order, and holes are formed among the multiple seed crystal structures and communicated with one another; lifting-off the multiple seed crystal structures and the semiconductor film layer from the first substrate layer; and bonding a side of the multiple seed crystal structures facing away from the semiconductor film layer with a second substrate layer to complete processes of the semiconductor film lifting-off and the substrate transfer. The method can be compatible with various epitaxial substrate materials, and can also retain smooth surface of the device epitaxial layer film without affecting the subsequent process of growing other functional layers for preparing devices on the epitaxial layer film.

A new approach for fabricating N-polar devices without the need of developing N-polar Al.sub.xGa.sub.1-xN buffer layers over substrates such as sapphire, SiC, GaN, AlN and Al.sub.xGa.sub.1-xN using a simplified material growth process.

A method of forming a silicon film on a substrate having a fine pattern includes performing surface treatment with an adhesion promoter on the substrate having the fine pattern, forming a coating film by applying a silane polymer solution to the substrate on which the surface treatment has been performed, and heating the coating film.

In a semiconductor manufacturing method, a mask is disposed on a semiconductor layer or semiconductor substrate. The semiconductor layer or semiconductor substrate is etched in an area delineated by the mask to form a cavity. With the mask disposed on the semiconductor layer or semiconductor substrate, the cavity is lined to form a containment structure. With the mask disposed on the semiconductor layer or semiconductor substrate, the containment structure is filled with a base semiconductor material. After filling the containment structure with the base semiconductor material, the mask is removed. At least one semiconductor device is fabricated in and/or on the base semiconductor material deposited in the containment structure.