A method of producing a crystalline silicon film includes forming a first silicon film that is amorphous at formation, forming a doped film of silicon or germanium on the first silicon film, the doped film being amorphous at formation; and annealing the structure to crystallize the doped film and the first silicon film. A method of producing a crystalline silicon film includes forming a Si.sub.x1Ge.sub.1-x1 film on a substrate, forming a Si.sub.x2Ge.sub.1-x2 film on the Si.sub.x1Ge.sub.1-x1 film, the Si.sub.x1Ge.sub.1-x1 film being amorphous at formation and having a first thermal budget for crystallization, the Si.sub.x2Ge.sub.1-x2 film being amorphous at formation and having a second thermal budget for crystallization, the second thermal budget being lower than the first thermal budget, forming a silicon film on the Si.sub.x2Ge.sub.1-x2 film, the silicon film being amorphous at formation; and annealing to crystallize the Si.sub.x1Ge.sub.1-x1 film, the Si.sub.x2Ge.sub.1-x2 film, and the silicon film.

A method for manufacturing a vertical JFET includes providing a III-nitride substrate having a first conductivity type and forming a first III-nitride layer coupled to the III-nitride substrate. The first III-nitride layer is characterized by a first dopant concentration and the first conductivity type. The method also includes forming a plurality of trenches within the first III-nitride layer and epitaxially regrowing a second III-nitride structure in the trenches. The second III-nitride structure is characterized by a second conductivity type. The method further includes forming a plurality of III-nitride fins, each coupled to the first III-nitride layer, wherein the plurality of III-nitride fins are separated by one of a plurality of recess regions, and epitaxially regrowing a III-nitride gate layer in the recess regions. The III-nitride gate layer is coupled to the second III-nitride structure and the III-nitride gate layer is characterized by the second conductivity type.

Described herein are systems and methods of utilizing nanochannels generated in the sacrificial layer of a semiconductor substrate to increase epitaxial lift-off speeds and facilitate reusability of GaAs substrates. The provided systems and methods may utilize unique nanochannel geometries to increase the surface area exposed to the etchant and further decrease etch times.

A single crystal semiconductor includes a strain compensation layer; an amorphous substrate disposed on the strain compensation layer; a lattice matching layer disposed on the amorphous substrate and including two or more single crystal layers; and a single crystal semiconductor layer disposed on the lattice matching layer, the lattice matching layer including a direction control film disposed on the amorphous substrate and including a single crystal structure, and a buffer layer including a material different from that of the direction control film, the buffer layer being disposed on the direction control film and including a single crystal structure.

A bulk acoustic wave resonator and a method of manufacturing the same are provided. The bulk acoustic wave resonator includes: a first carrier substrate; a barrier layer on a main surface of the first carrier substrate and configured to prevent an undesired conductive channel from being generated due to charge accumulation on the main surface; a buffer layer on a side of the barrier layer away from the first carrier substrate; a piezoelectric layer on a side of the buffer layer away from the barrier layer; a first electrode and a second electrode on opposite sides of the piezoelectric layer; a first passivation layer and a second passivation layer, respectively covering sidewalls of the first electrode and the second electrode; a dielectric layer between the first passivation layer and the buffer layer, wherein a first cavity is provided between the first passivation layer and the dielectric layer.

The present invention is a laminate including: a crystal substrate; a middle layer formed on a main surface of the crystal substrate, the middle layer containing a mixture of an amorphous region in an amorphous phase and a crystal region in a crystal phase having a corundum structure mainly made of a first metal oxide; and a crystal layer formed on the middle layer and having a corundum structure mainly made of a second metal oxide. Thus, provided is a laminate having high-quality corundum-structured crystal with sufficiently suppressed crystal defects.

The disclosure provides a film forming method that enables to obtain an epitaxial film with reduced defects such as dislocations due to a reduced facet growth industrially advantageously, even if the epitaxial film has a corundum structure. When forming an epitaxial film on a crystal-growth surface of a corundum-structured crystal substrate directly or via another layer, using the crystal substrate having an uneven portion on the crystal-growth surface of the crystal substrate, generating and floating atomized droplets by atomizing a raw material solution including a metal; carrying the floated atomized droplets onto a surface of the crystal substrate by using a carrier gas; and causing a thermal reaction of the atomized droplets in a condition of a supply rate limiting state.

An integrated circuit structure includes a first transistor, an interconnect structure, a first dielectric layer, polycrystalline plugs, a semiconductor structure and a second transistor. The first transistor is formed on a substrate. The interconnect structure is over the first transistor. The first dielectric layer is over the interconnect structure. The polycrystalline plugs extend from a top surface of the dielectric layer into the dielectric layer. The semiconductor structure is disposed over the first dielectric layer. The second transistor is formed on the semiconductor structure.

A semiconductor structure and a method for fabricating the semiconductor structure are provided. The method includes providing a substrate; forming a silicon layer on the substrate, wherein an edge region of the top surface of the substrate is exposed from the silicon layer; epitaxially growing a GaN-based semiconductor material on the silicon layer and the substrate to form a GaN-based semiconductor layer on the silicon layer and a plurality of GaN-based nodules on the edge region of the top surface of the substrate; and performing a first dry etch step to remove the GaN-based nodules, wherein performing the first dry etch step includes applying a first bias power that is equal to or higher than 1500 W.

A method of producing a polycrystalline silicon TFT includes forming nickel patterns on a substrate, forming a phosphorus doped silicon layer over the substrate and nickel patterns, and forming an intrinsic silicon layer on the phosphorus doped silicon layer. Alternatively, the intrinsic silicon layer can be formed on the substrate, the phosphorus doped silicon layer on the intrinsic silicon layer, and the nickel patterns on the phosphorus doped silicon layer. The structure is annealed to crystallize the phosphorus doped silicon and intrinsic silicon layers. A method of forming a crystalline silicon layer of a TFT device includes forming a first silicon film, forming a phosphorus doped silicon film on the first silicon film, forming a nickel film on the phosphorus doped silicon film, and annealing the structure to crystallize the phosphorus doped silicon and first silicon films. The first silicon and phosphorous doped silicon films are amorphous at formation.