A method of manufacturing a stacked structure includes forming a first metal buffer layer including crystal grains on a base substrate, forming a second metal buffer material layer on the first metal buffer layer, and crystallizing the second metal buffer material layer to form a second metal buffer layer, wherein the second metal buffer material layer includes crystal grains, and a density of the crystal grains of the second metal buffer material layer is lower than a density of the crystal grains of the first metal buffer layer.

AlN templates, with excellent thermal conductivity formed via Air-pocket assisted Pulsed Lateral Epitaxy that possess reverse grading (from AlGaN to GaN) in the contacts region, which for the N-polar epilayers should lead to electron accumulation.

A step of preparing a base substrate of a single crystal of a group III nitride semiconductor; a growth inhibition layer forming step of performing in situ formation of a growth inhibition layer over the entire main surface of the base substrate in a vapor phase growth apparatus; a first step of growing a first layer by epitaxially growing a single crystal of a group III nitride semiconductor on the main surface of the base substrate via openings in the growth inhibition layer by using the vapor phase growth apparatus where the base substrate on which the growth inhibition layer has been formed is placed in the vapor phase growth apparatus; and a second step of growing a second layer with a mirror surface by epitaxially growing a single crystal of a group III nitride semiconductor on the first layer so as to make the inclined interfaces disappear.

Methods, systems, and apparatuses are described for a CMOS compatible substrate having multiple stacks of semiconductor layers. The multiple stacks, at least, each include i) a layer of a tellurium based semiconductor layer on top of ii) a porous silicon layer. The porous silicon layer is a compliant layer to accept structural defects from the tellurium based semiconductor layer into the porous silicon layer. The multiple stacks are grown on the CMOS compatible substrate.

Provided are a conductive structure and a method of controlling a work function of metal. The conductive structure includes a conductive material layer including metal and a work function control layer for controlling a work function of the conductive structure by being bonded to the conductive material layer. The work function control layer includes a two-dimensional material with a defect.

Provided is a method for manufacturing a monocrystalline substrate, the method including: a process of forming a seed layer on a base charged into a monocrystalline growth apparatus; a process of taking the base, on which the seed layer is formed, out of the monocrystalline growth apparatus and irradiating laser onto the seed layer from a lower side of the base to form a separation layer having a plurality of voids; a process of charging the base, on which the separation layer is formed, into the monocrystalline growth apparatus to form a monocrystalline layer on the separation layer; and a separation process of taking the base, on which the separation layer and the monocrystalline layer are formed, out of the monocrystalline growth apparatus to separate the monocrystalline layer from the base. Therefore, the monocrystalline layer may be grown on the flat surface of the separation layer, and the monocrystalline substrate having the excellent crystallinity and suppressed in occurrence of the defects may be prepared. That is, the monocrystalline substrate having the excellent crystallinity and suppressed in occurrence of the defects while omitting the planarization process for planarizing the surface of the flat separation layer may be prepared.

A method for manufacturing a nitride semiconductor substrate, including: a step of preparing a base substrate; a step of forming a mask layer having a plurality of openings on the main surface of the base substrate; a first step of growing a first layer whose surface is composed only of inclined interfaces; and a second step of epitaxially growing a single crystal of a group III nitride semiconductor on the first layer, making the inclined interfaces disappear, and growing a second layer having a mirror surface, wherein in the first step, at least one valley and a plurality of tops are formed at an upper side of each of the plurality of openings of the mask layer by forming a plurality of concaves on a top surface of the single crystal and making the (0001) plane disappear.

Aspects of the disclosure provide a method including depositing an underlayer comprising silicon oxide over a substrate, depositing a polysilicon liner on the underlayer, and depositing an amorphous silicon layer on the polysilicon liner. Aspects of the disclosure provide a device intermediate including a substrate, an underlayer comprising silicon oxide formed over the substrate, a polysilicon liner disposed on the underlayer, and an amorphous silicon layer disposed on the polysilicon liner.

Apparatuses and methods relating to semiconductor layer structures are disclosed. A method for producing a semiconductor layer structure ay involve providing a Si substrate comprising a top surface, forming a first semiconductor layer on the substrate, the first semiconductor layer comprising a plurality of vertical nanowire structures, arranged perpendicularly to the top surface of the substrate, the first semiconductor layer comprising AIN, and epitaxially growing a second semiconductor layer which laterally and vertically encloses the plurality of vertical nanowire structures thereby encapsulating dislocations in shells around the nanowires, wherein the second semiconductor layer comprises Al.sub.xGa.sub.1-xN, wherein 0:x:0.95.

A semiconductor device includes a semiconductor fin, a gate structure, a doped semiconductor layer, and a dielectric structure. The semiconductor fin has a top portion and a lower portion extending from the top portion to a substrate. The gate structure extends across the semiconductor fin. The doped semiconductor layer interfaces the top portion of the semiconductor fin. In a cross-section taken along a lengthwise direction of the gate structure, the doped semiconductor layer has an outer profile conformal to a profile of the top portion of the semiconductor fin.