Patent classifications
H01L21/02573
METHOD FOR MANUFACTURING SEMICONDUCTOR DEVICE
Provided is a method for manufacturing a semiconductor device whose electric characteristics are prevented from being varied and whose reliability is improved. In the method, an insulating film is formed over an oxide semiconductor film, a buffer film is formed over the insulating film, oxygen is added to the buffer film and the insulating film, a conductive film is formed over the buffer film to which oxygen is added, and an impurity element is added to the oxide semiconductor film using the conductive film as a mask. An insulating film containing hydrogen and overlapping with the oxide semiconductor film may be formed after the impurity element is added to the oxide semiconductor film.
SEMICONDUCTOR DEVICE
A semiconductor device with favorable electrical characteristics is provided. A highly reliable semiconductor device is provided. A semiconductor device with stable electrical characteristics is provided. The semiconductor device includes a semiconductor layer, a first insulating layer, a metal oxide layer, a conductive layer, and an insulating region. The first insulating layer covers a top surface and a side surface of the semiconductor layer, and the conductive layer is positioned over the first insulating layer. The metal oxide layer is positioned between the first insulating layer and the conductive layer, and an end portion of the metal oxide layer is positioned on an inner side than an end portion of the conductive layer. The insulating region is positioned adjacent to the metal oxide layer and positioned between the first insulating layer and the conductive layer. Furthermore, the semiconductor layer includes a first region, a pair of second regions, and a pair of third regions. The first region overlaps with the metal oxide layer and the conductive layer. The second regions are positioned to put the first region sandwiched therebetween and to overlap with the insulating region and the conductive layer. The third regions are positioned to the first region and the pair of second regions sandwiched therebetween and not to overlap with the conductive layer. The third regions preferably include a portion having lower resistance than the first region. The second regions preferably include a portion having higher resistance than the third regions.
Rare earth nitride structures and devices and method for removing a passivating capping
The present invention concerns a structure or device comprising a rare earth nitride material, and a removable capping for passivating the rare earth nitride material.
Method of fabricating thin, crystalline silicon film and thin film transistors
A method of producing a crystalline silicon film includes forming a first silicon film that is amorphous at formation, forming a doped film of silicon or germanium on the first silicon film, the doped film being amorphous at formation; and annealing the structure to crystallize the doped film and the first silicon film. A method of producing a crystalline silicon film includes forming a Si.sub.x1Ge.sub.1-x1 film on a substrate, forming a Si.sub.x2Ge.sub.1-x2 film on the Si.sub.x1Ge.sub.1-x1 film, the Si.sub.x1Ge.sub.1-x1 film being amorphous at formation and having a first thermal budget for crystallization, the Si.sub.x2Ge.sub.1-x2 film being amorphous at formation and having a second thermal budget for crystallization, the second thermal budget being lower than the first thermal budget, forming a silicon film on the Si.sub.x2Ge.sub.1-x2 film, the silicon film being amorphous at formation; and annealing to crystallize the Si.sub.x1Ge.sub.1-x1 film, the Si.sub.x2Ge.sub.1-x2 film, and the silicon film.
High efficiency ultraviolet light emitting diode with electron tunnelling
A method of growing an AlGaN semiconductor material utilizes an excess of Ga above the stoichiometric amount typically used. The excess Ga results in the formation of band structure potential fluctuations that improve the efficiency of radiative recombination and increase light generation of optoelectronic devices, in particular ultraviolet light emitting diodes, made using the method. Several improvements in UV LED design and performance are also provided for use together with the excess Ga growth method. Devices made with the method can be used for water purification, surface sterilization, communications, and data storage and retrieval.
NANOWIRE DEVICE
A composition of matter comprising: a graphene layer carried directly on a sapphire, Si, SiC, Ga.sub.2O.sub.3 or group III-V semiconductor substrate; wherein a plurality of holes are present through said graphene layer; and wherein a plurality of nanowires or nanopyramids are grown from said substrate in said holes, said nanowires or nanopyramids comprising at least one semiconducting group III-V compound.
Devices Having a Semiconductor Material That Is Semimetal in Bulk and Methods of Forming the Same
Devices, and methods of forming such devices, having a material that is semimetal when in bulk but is a semiconductor in the devices are described. An example structure includes a substrate, a first source/drain contact region, a channel structure, a gate dielectric, a gate electrode, and a second source/drain contact region. The substrate has an upper surface. The channel structure is connected to and over the first source/drain contact region, and the channel structure is over the upper surface of the substrate. The channel structure has a sidewall that extends above the first source/drain contact region. The channel structure comprises a bismuth-containing semiconductor material. The gate dielectric is along the sidewall of the channel structure. The gate electrode is along the gate dielectric. The second source/drain contact region is connected to and over the channel structure.
Method of manipulating deposition rates of poly-silicon and method of manufacturing a SiGe HBT device
A method of manipulating deposition rates of poly-silicon and a method of manufacturing a silicon-germanium (SiGe) heterojunction bipolar transistor (HBT) device are provided. The method of manipulating deposition rates of poly-silicon includes: providing a substrate, where a first surface of the substrate includes at least two of an oxide material region, a silicon nitride material region and a silicon material region; performing a first treatment on the first surface of the substrate, so as to manipulate the deposition rates of poly-silicon on different regions of the first surface to be closer; and forming a poly-silicon layer on the first surface of the substrate.
METHOD AND APPARATUS FOR PRODUCING SiC SUBSTRATE
An apparatus for producing an SiC substrate, by which an SiC substrate having a thin base substrate layer is able to be produced, while suppressing deformation or breakage, includes a main container which is capable of containing an SiC base substrate, and which produces a vapor pressure of a vapor-phase species containing elemental Si and a vapor-phase species containing elemental C within the internal space by means of heating; and a heating furnace which contains the main container and heats the main container so as to form a temperature gradient, while producing a vapor pressure of a vapor-phase species containing elemental Si within the internal space. The main container has a growth space in which a growth layer is formed on one surface of the SiC base substrate, and an etching space in which the other surface of the SiC base substrate is etched.
Devices having a semiconductor material that is semimetal in bulk and methods of forming the same
Devices, and methods of forming such devices, having a material that is semimetal when in bulk but is a semiconductor in the devices are described. An example structure includes a substrate, a first source/drain contact region, a channel structure, a gate dielectric, a gate electrode, and a second source/drain contact region. The substrate has an upper surface. The channel structure is connected to and over the first source/drain contact region, and the channel structure is over the upper surface of the substrate. The channel structure has a sidewall that extends above the first source/drain contact region. The channel structure comprises a bismuth-containing semiconductor material. The gate dielectric is along the sidewall of the channel structure. The gate electrode is along the gate dielectric. The second source/drain contact region is connected to and over the channel structure.