An integrated circuit device includes a fin-type active area along a first horizontal direction on a substrate, a device isolation layer on opposite sidewalls of the fin-type active area, a gate structure along a second horizontal direction crossing the first horizontal direction, the gate structure being on the fin-type active area and on the device isolation layer, and a source/drain area on the fin-type active area, the source/drain area being adjacent to the gate structure, and including an outer blocking layer, an inner blocking layer, and a main body layer sequentially stacked on the fin-type active area, and each of the outer blocking layer and the main body layer including a Si1-xGex layer, where x≠0, and the inner blocking layer including a Si layer.

A method and a wafer processing furnace for forming an epitaxial stack on a plurality of substrates is provided. In a preferred embodiment, the method comprises providing the plurality of substrates to a process chamber. A plurality of deposition cycles is executed, thereby forming the epitaxial stack on the plurality of substrates. The epitaxial stack comprises a plurality of epitaxial pairs, wherein the epitaxial pairs each comprises a first epitaxial layer and a second epitaxial layer, the second epitaxial layer being different from the first epitaxial layer. Each deposition cycle comprises a first deposition pulse and a second deposition pulse. The first deposition pulse comprises a provision of a first reaction gas mixture to the process chamber, thereby forming the first epitaxial layer. The second deposition pulse comprises a provision of a second reaction gas mixture to the process chamber, thereby forming the second epitaxial layer. The first deposition pulse or the second deposition pulse further comprises a provision of a dopant precursor gas to the process chamber.

Embodiments of the present invention generally relate to methods of epitaxially growing boron-containing structures. In an embodiment, a method of depositing a structure comprising boron and a Group IV element on a substrate is provided. The method includes heating the substrate at a temperature of about 300° C. or more within a chamber, the substrate having a dielectric material and a single crystal formed thereon. The method further includes flowing a first process gas and a second process gas into the chamber, wherein: the first process gas comprises at least one boron-containing gas comprising a haloborane; and the second process gas comprises at least one Group IV element-containing gas. The method further includes exposing the substrate to the first and second process gases to epitaxially and selectively deposit the structure comprising boron and the Group IV element on the single crystal.

A method and a wafer processing furnace for forming an epitaxial stack on a plurality of substrates is provided. In a preferred embodiment, the method comprises providing plurality of substrates to a process chamber. A plurality of deposition cycles are executed, thereby forming the epitaxial stack on the plurality of substrates. The epitaxial comprises a plurality of epitaxial pairs, each pair comprising a first epitaxial layer and a second epitaxial layer. The deposition cycle comprises a first deposition pulse and a second deposition pulse. The first deposition pulse comprises a provision of a first reaction gas mixture to the process chamber, thereby forming the first epitaxial layer and the second deposition pulse comprises a provision of a second reaction gas mixture to the process chamber, thereby forming the second epitaxial layer

A method of forming an epitaxial stack on a plurality of substrates is provided. In a preferred embodiment, the method comprises providing a semiconductor processing apparatus. This semiconductor processing apparatus comprises a process chamber and a carousel for stationing a wafer boat before or after processing in the process chamber. The method further comprises loading the wafer boat into the process chamber, the wafer boat comprising the plurality of substrates. The method further comprises processing the plurality of substrates in the process chamber, thereby forming, on the plurality of substrates, the epitaxial stack. This epitaxial stack has a pre-determined thickness. The processing comprises unloading the wafer boat, one or more times, from the process chamber to the carousel until the epitaxial stack reaches the pre-determined thickness.

A method for making a multilayered device on an engineered substrate having a substrate coefficient of thermal expansion includes growing a buffer layer on the engineered substrate, and growing a first epitaxial layer on the buffer layer. The first epitaxial layer is characterized by an epitaxial coefficient of thermal expansion substantially equal to the substrate coefficient of thermal expansion.

A structure including a three-dimensionally stretchable single crystalline semiconductor membrane located on a substrate is provided. The structure is formed by providing a three-dimensional (3D) wavy silicon germanium alloy layer on a silicon handler substrate. A single crystalline semiconductor material membrane is then formed on a physically exposed surface of the 3D wavy silicon germanium alloy layer. A substrate is then formed on a physically exposed surface of the single crystalline semiconductor material membrane. The 3D wavy silicon germanium alloy layer and the silicon handler substrate are thereafter removed providing the structure.

A method for manufacturing a semiconductor structure is provided. The method includes a III-V semiconductor device in a first region of a base substrate and a further device in a second region of the base substrate. The method includes: (a) obtaining a base substrate comprising the first region and the second region, different from the first region; (b) providing a buffer layer over a surface of the base substrate at least in the first region, wherein the buffer layer comprises at least one monolayer of a first two-dimensional layered crystal material; (c) forming, over the buffer layer in the first region, and not in the second region, a III-V semiconductor material; and (d) forming, in the second region, at least part of the further device. A semiconductor structure is also provided.

The embodiments described herein are directed to a method for reducing fin oxidation during the formation of fin isolation regions. The method includes providing a semiconductor substrate with an n-doped region and a p-doped region formed on a top portion of the semiconductor substrate; epitaxially growing a first layer on the p-doped region; epitaxially growing a second layer different from the first layer on the n-doped region; epitaxially growing a third layer on top surfaces of the first and second layers, where the third layer is thinner than the first and second layers. The method further includes etching the first, second, and third layers to form fin structures on the semiconductor substrate and forming an isolation region between the fin structures.

The present invention relates to a method for manufacturing a diamond substrate, and more particularly, to a method of growing diamond after forming a structure of an air gap having a crystal correlation with a lower substrate by heat treatment of a photoresist pattern and an air gap forming film material on a substrate such as sapphire (Al.sub.2O.sub.3). Through such a method, a process is simplified and the cost is lowered when large-area/large-diameter single crystal diamond is heterogeneously grown, stress due to differences in a lattice constant and a coefficient of thermal expansion between the heterogeneous substrate and diamond is relieved, and an occurrence of defects or cracks is reduced even when a temperature drops, such that a high-quality single crystal diamond substrate may be manufactured and the diamond substrate may be easily self-separated from the heterogeneous substrate.