Embodiments relate to fabricating a wafer including a thin, high-quality single crystal GaN layer serving as a template for formation of additional GaN material. A bulk ingot of GaN material is subjected to implantation to form a subsurface cleave region. The implanted bulk material is bonded to a substrate having lattice and/or Coefficient of Thermal Expansion (CTE) properties compatible with GaN. Examples of such substrate materials can include but are not limited to AlN and Mullite. The GaN seed layer is transferred by a controlled cleaving process from the implanted bulk material to the substrate surface. The resulting combination of the substrate and the GaN seed layer, can form a template for subsequent growth of overlying high quality GaN. Growth of high-quality GaN can take place utilizing techniques such as Liquid Phase Epitaxy (LPE) or gas phase epitaxy, e.g., Metallo-Organic Chemical Vapor Deposition (MOCVD) or Hydride Vapor Phase Epitaxy (HVPE).

Provided are a p-type oxide semiconductor, a method of forming the p-type oxide semiconductor, and a transistor with the p-type oxide semiconductor. The p-type oxide semiconductor includes an alkali metal and a tin oxide.

A vertical channel field-effect transistor is taught. The vertical channel field-effect transistor comprises a primary substrate and a secondary substrate. A bottom conducting layer is provided on the primary substrate. A top conducting layer is transferred from a secondary substrate to the primary substrate by using an insulating adhesive layer. The thickness of the insulating adhesive layer defines the channel length. The portion of the top conducting layer which is over the bottom conducting layer defines the maximum possible channel. At least one semiconducting layer is provided on and around a perimeter of at least a portion of the channel width. At least one insulating layer is provided on at least a portion of the at least one semiconducting layer. At least one gate conducting layer provided on at least a portion of the at least one insulating layer.

A layer of additive material is formed in a circular printing area on a substrate using additive sources distributed across a printing zone. The additive sources form predetermined discrete amounts of the additive material. The substrate and the additive sources are rotated with respect to each other around a center of rotation, so that a pattern of the additive material is formed in a circular printing area on the substrate. Each additive source receives actuation waveforms at an actuation frequency that is proportional to a distance of the additive source from the center of rotation. The actuation waveforms include formation signals, with a maximum of one formation signal in each cycle of the actuation frequency. The formation signals result in the additive sources forming the predetermined discrete amounts of the additive material on the substrate.

The invention provides a metal oxide semiconductor layer forming composition containing a solvent represented by formula [1]: ##STR00001##
(wherein R.sub.1 represents a C2 to C3 linear or branched alkylene group, and R.sub.2 represents a C1 to C3 linear or branched alkyl group) and an inorganic metal salt.

A field effect transistor including a dielectric layer on a substrate, a nano-structure material (NSM) layer on the dielectric layer, a source electrode and a drain electrode formed on the NSM layer, a gate dielectric formed on at least a portion of the NSM layer between the source electrode and the drain electrode, a T-shaped gate electrode formed between the source electrode and the drain electrode, where the NSM layer forms a channel of the FET, and a doping layer on the NSM layer extending at least from the sidewall of the source electrode to a first sidewall of the gate dielectric, and from a sidewall of the drain electrode to a second sidewall of the gate dielectric.

A field effect transistor including a dielectric layer on a substrate, a nano-structure material (NSM) layer on the dielectric layer, a source electrode and a drain electrode formed on the NSM layer, a gate dielectric formed on at least a portion of the NSM layer between the source electrode and the drain electrode, a T-shaped gate electrode formed between the source electrode and the drain electrode, where the NSM layer forms a channel of the FET, and a doping layer on the NSM layer extending at least from the sidewall of the source electrode to a first sidewall of the gate dielectric, and from a sidewall of the drain electrode to a second sidewall of the gate dielectric.

The present invention provides a method for producing a Group III nitride semiconductor crystal and a GaN substrate, in which the transfer of dislocation density or the occurrence of cracks can be certainly reduced on a growth substrate, and the Group III nitride semiconductor crystal can be easily separated from a seed crystal. A mask layer is formed on a GaN substrate, to thereby form an exposed portion of the GaN substrate, and an unexposed portion of the GaN substrate. Through a flux method, a GaN layer is formed on the exposed portions of the GaN substrate in a molten mixture containing at least Group III metal and Na. At that time, non-crystal portions containing the components of the molten mixture are formed on the mask layer so as to be covered with the GaN layer grown on the GaN substrate and the mask layer.

The present invention discloses an electronic device using a group III nitride substrate fabricated via the ammonothermal method. By utilizing the high-electron concentration of ammonothermally grown substrates having the dislocation density less than 10.sup.5 cm.sup.2, combined with a high-purity active layer of Ga.sub.1-x-yAl.sub.xIn.sub.yN (0x1, 0y1) grown by a vapor phase method, the device can attain high level of breakdown voltage as well as low on-resistance. To realize a good matching between the ammonothermally grown substrate and the high-purity active layer, a transition layer is optionally introduced. The active layer is thicker than a depletion region created by a device structure in the active layer.

Example embodiments relate to an electronic device having a graphene-semiconductor multi-junction and a method of manufacturing the electronic device. The electronic device includes a graphene layer having at least one graphene protrusion and a semiconductor layer that covers the graphene layer. A side surface of each of the at least one graphene protrusion may be uneven, may have a multi-edge, and may be a stepped side surface. The graphene layer includes a plurality of nanocrystal graphenes. The graphene layer includes a lower graphene layer having a plurality of nanocrystal graphenes and the at least one graphene protrusion that is formed on the lower graphene layer. The semiconductor layer may include a transition metal dichalcogenide (TMDC) layer. Each of the at least one graphene protrusion may include a plurality of nanocrystal graphenes.