A vertical memory device, including: a substrate including a cell array region and an extension region; gate electrodes stacked on each other with a plurality of levels, wherein each of the gate electrodes includes a pad, and wherein the pads disposed on the gate electrodes form at least one staircase structure on the extension region of the substrate; a channel extending in a first direction on the cell array region of the substrate through at least one of the gate electrodes; and dummy gate electrode groups disposed on the extension region of the substrate, wherein the dummy gate electrode groups includes dummy gate electrodes, wherein each of the dummy gate electrodes are spaced apart from a corresponding gate electrode among the gate electrodes stacked at a same level, wherein the dummy gate electrode groups are spaced apart from each other in a second direction.

A nonpolar III-nitride film grown on a miscut angle of a substrate, in order to suppress the surface undulations, is provided. The surface morphology of the film is improved with a miscut angle towards an a-axis direction comprising a 0.15° or greater miscut angle towards the a-axis direction and a less than 30° miscut angle towards the a-axis direction.

In one aspect, a method for forming a 3D memory device is disclosed. A selective epitaxial sacrificial layer is formed above a substrate, and a dielectric stack is formed above the selective epitaxial sacrificial layer. A first opening extending vertically through the dielectric stack and the selective epitaxial sacrificial layer is formed. A portion of the first opening extending vertically through the selective epitaxial sacrificial layer is enlarged. A memory film and a semiconductor channel are subsequently formed in this order along sidewalls and a bottom surface of the first opening. The selective epitaxial sacrificial layer is removed to form a cavity exposing a portion of the memory film. The portion of the memory film exposed in the cavity is removed to expose a portion of the semiconductor channel. A selective epitaxial layer is epitaxially grown from the substrate to fill the cavity and be in contact with the portion of the semiconductor channel.

Embodiments of the present disclosure generally relate to substrate supports for process chambers and RF grounding configurations for use therewith. Methods of grounding RF current are also described. A chamber body at least partially defines a process volume therein. A first electrode is disposed in the process volume. A pedestal is disposed opposite the first electrode. A second electrode is disposed in the pedestal. An RF filter is coupled to the second electrode through a conductive rod. The RF filter includes a first capacitor coupled to the conductive rod and to ground. The RF filter also includes a first inductor coupled to a feedthrough box. The feedthrough box includes a second capacitor and a second inductor coupled in series. A direct current (DC) power supply for the second electrode is coupled between the second capacitor and the second inductor.

A method is provided for fabricating a semiconductor structure. The method includes forming a base substrate including a substrate and a stress layer formed in the substrate, where a top surface of the stress layer is higher than a surface of the substrate. The method also includes forming a first cover layer, where a first growth rate difference exists between growth rates of the first cover layer on the top surface of the stress layer and the first cover layer on a side surface of the stress layer. Further, the method includes forming a second cover layer, where a second growth rate difference exists between growth rates of the second cover layer on the top surface of the stress layer and the second cover layer on the side surface of the stress layer, and the second growth rate difference is larger than the first growth rate difference.

A method is provided for fabricating a semiconductor structure. The method includes providing a substrate including a first region for forming a first transistor and a second region for forming a second transistor. The method also includes forming a first stress layer in the substrate in the first region and a second stress layer in the substrate in the second region, wherein top surfaces of the first stress layer and the second stress layer are above a surface of the substrate. Further, the method includes forming a cover layer on each of the first stress layer and the second stress layer, and removing portions of the cover layer formed on adjacent side surfaces of the first stress layer and the second stress layer.

A method for producing a semiconductor chip (100) is provided, in which, during a growth process for growing a first semiconductor layer (1), an inhomogeneous lateral temperature distribution is created along at least one direction of extent of the growing first semiconductor layer (1), such that a lateral variation of a material composition of the first semiconductor layer (1) is produced. A semiconductor chip (100) is additionally provided.

A MEMS sensor includes: a first substrate having a cavity partially exposed on the surface of the first substrate; an electrode of a sensor element provided on the first substrate and arranged in the cavity; a support portion provided on the first substrate and configured to support the electrode; an element isolation portion formed on the first substrate so as to cover the support portion and configured to electrically isolate the electrode and the support portion from each other; an epitaxial growth layer formed on the electrode and the element isolation portion of the first substrate; and a second substrate bonded to the first substrate and configured to cover the sensor element, wherein the epitaxial growth layer has a monocrystalline portion arranged on the electrode and a polycrystalline portion arranged on the element isolation portion.

An integrated circuit structure includes a gate stack over a semiconductor substrate, and an opening extending into the semiconductor substrate, wherein the opening is adjacent to the gate stack. A first silicon germanium region is in the opening, wherein the first silicon germanium region has a first germanium percentage. A second silicon germanium region is over the first silicon germanium region, wherein the second silicon germanium region has a second germanium percentage higher than the first germanium percentage. A third silicon germanium region is over the second silicon germanium region, wherein the third silicon germanium region has a third germanium percentage lower than the second germanium percentage.

A memory array comprising strings of memory cells comprises laterally-spaced memory blocks individually comprising a vertical stack comprising alternating insulative tiers and conductive tiers. Operative channel-material strings of memory cells extend through the insulative tiers and the conductive tiers. Upper masses comprise first material laterally-between and longitudinally-spaced-along immediately-laterally-adjacent of the memory blocks and second material laterally-between and longitudinally-spaced-along the immediately-laterally-adjacent memory blocks longitudinally-between and under the upper masses. The second material is of different composition from that of the first material. The second material comprises insulative material. Other embodiments, including method, are disclosed.