A semiconductor device including a nanostructure, including a planar layer of a III-nitride semiconductor crystal, which layer includes an array of epitaxially grown nanowire structures, and semiconductor material which is redistributed from said nanowire structures in a reformation step after epitaxial growth, arranged to fill out a spacing between the nanowire structures, where the array of nanowire structures and the semiconductor material form a coherent layer.

A method for manufacturing a semiconductor device is provided. The method includes forming at least one epitaxial layer over a substrate; forming a mask over the epitaxial layer; patterning the epitaxial layer into a semiconductor fin; depositing a semiconductor capping layer over the semiconductor fin and the mask, wherein the semiconductor capping layer has a first portion that is amorphous on a sidewall of the mask; performing a thermal treatment such that the first portion of the semiconductor capping layer is converted from amorphous into crystalline; forming an isolation structure around the semiconductor fin; and forming a gate structure over the semiconductor fin.

A transistor includes a first gate electrode, a first capping layer, a crystalline semiconductor oxide layer, a second capping layer, a first gate dielectric layer, and source/drain contacts. The first capping layer, the crystalline semiconductor oxide layer, and the second capping layer are sequentially disposed over the first gate electrode. Sidewalls of the second capping layer are aligned with sidewalls of the crystalline semiconductor oxide layer. The first gate dielectric layer is located between the first gate electrode and the first capping layer. The source/drain contacts are disposed on the second capping layer. The crystalline semiconductor oxide layer and the source/drain contacts are located on two opposite sides of the second capping layer.

Aspects of the disclosure provide methods for polysilicon characterization. The method includes receiving image data of a polysilicon structure formed on a sample substrate. The image data is in a spatial domain and is generated by transmission electron microscopy (TEM). Further, the method includes extracting frequency spectrum of the image data in a frequency domain. Then, the method includes selecting a subset of the frequency spectrum that corresponds to characteristic of first crystal grains that are of a first orientation, and transforming the selected subset of the frequency spectrum to the spatial domain to construct a first spatial image for the first crystal grains of the first orientation.

Methods, apparatuses, and systems related to semiconductor structure formation are described. An example method includes forming an opening through silicon (Si) material, formed over a semiconductor substrate, to a first depth to form pillars of Si material. The example method further includes depositing an isolation material within the opening to fill the opening between the Si pillars. The example method further includes removing a portion of the isolation material from between the pillars to a second depth to create a second opening between the pillars and defining inner sidewalls between the pillars. The example method further includes depositing an enhancer material over a top surface of the pillars and along the inner sidewalls of the pillars down to a top portion of the isolation material.

A method of scaling a nonvolatile trapped-charge memory device and the device made thereby is provided. In an embodiment, the method includes forming a channel region including polysilicon electrically connecting a source region and a drain region in a substrate. A tunneling layer is formed on the substrate over the channel region by oxidizing the substrate to form an oxide film and nitridizing the oxide film. A multi-layer charge trapping layer including an oxygen-rich first layer and an oxygen-lean second layer is formed on the tunneling layer, and a blocking layer deposited on the multi-layer charge trapping layer. In one embodiment, the method further includes a dilute wet oxidation to densify a deposited blocking oxide and to oxidize a portion of the oxygen-lean second layer.

A method includes forming a semiconductor structure. The structure includes a first material, a blocking material, a second material in an amorphous form, and a third material in an amorphous form. The blocking material is disposed between the first material and the second material. At least the second material and the third material each comprise silicon and/or germanium. The structure is exposed to a temperature above a crystallization temperature of the third material and below a crystallization temperature of the second material. Semiconductor structures, memory devices, and systems are also disclosed.

A method to form a 2-Dimensional transistor channel may include depositing an amorphous layer comprising a 2-dimensional material, implanting an implant species into the amorphous layer; and annealing the amorphous layer after the implanting. As such, the amorphous layer may form a doped crystalline layer.

To provide a method of depositing a silicon film that can crystallize the silicon film at low temperature and in a short time, and also can deposit the silicon film with high flatness. A method of depositing a silicon film includes supplying a silicon-containing gas on a seed layer, depositing an amorphous silicon film on the seed layer, supplying chlorosilane gas to the amorphous silicon film, and crystallizing the amorphous silicon film while forming a chlorosilane cap layer on the amorphous silicon film.

A method of crystallizing an amorphous silicon film includes depositing the amorphous silicon film on a seed layer formed over a substrate while heating the amorphous silicon film at a first temperature, and forming a crystal nucleus in an outer layer of the amorphous silicon film by causing migration of silicon in the outer layer by heating the amorphous silicon film at a second temperature higher than the first temperature.