A method of fabricating a semiconductor device includes providing a substrate, implementing a growth procedure to form a semiconductor layer supported by the substrate, performing an anneal of the semiconductor layer, the anneal being conducted at a higher temperature than the growth procedure, and repeating the growth procedure and the anneal. The anneal is conducted at or above a decomposition temperature for the semiconductor layer.

A method of forming a semiconductor structure includes following operations. A substrate including a silicon (Si) layer is received. An amorphous germanium (Ge) layer is formed on the Si layer. A barrier layer is formed over the amorphous Ge layer. The substrate is annealed to transform the Si layer and the Ge layer to form a single crystalline SiGe layer. A Ge concentration is in a positive correlation with a ratio of a thickness of the Ge layer and a thickness of the Si layer.

A method for preparation of orientation-patterned (OP) templates comprising the steps of: depositing a first layer of a first material on a common substrate by a far-from-equilibrium process; and depositing a first layer of a second material on the first layer of the first material by a close-to-equilibrium process, wherein a first assembly is formed. The first material and the second material may be the same material or different materials. The substrate material may be Al.sub.2O.sub.3 (sapphire), silicon (Si), germanium (Ge), GaAs, GaP, GaSb, InAs, InP, CdTe, CdS, CdSe, or GaSe. The first material deposited on the common substrate may be one or more electronic or optical binary materials from the group consisting of AlN, GaN, GaP, InP, GaAs, InAs, AlAs, ZnSe, GaSe, ZnTe, CdTe, HgTe, GaSb, SiC, CdS, CdSe, or their ternaries or quaternaries. The far-from-equilibrium process is one of MOCVD and MBE, and the close-to-equilibrium process is HVPE.

A method for forming layers with silicon is disclosed. The layers may be created by positioning a substrate within a processing chamber, heating the substrate to a first temperature between 300 and 500° C. and introducing a first precursor into the processing chamber to deposit a first layer. The substrate may be heated to a second temperature between 400 and 600° C.; and, a second precursor may be introduced into the processing chamber to deposit a second layer. The first and second precursor may comprise silicon atoms and the first precursor may have more silicon atoms per molecule than the second precursor.

Embodiments provide for an optical modulator that includes a first silicon region, a polycrystalline silicon region; a gate oxide region joining the first silicon region to a first side of the polycrystalline region; and a second silicon region formed on a second side of the polycrystalline silicon region opposite to the first side, thereby defining an active region of an optical modulator between the first silicon region, the polycrystalline region, the gate oxide region, and the second silicon region. The polycrystalline silicon region may be between 0 and 60 nanometers thick, and may be formed or patterned to the desired thickness. The second silicon region may be epitaxially grown from the polycrystalline silicon region and patterned into a desired cross sectional shape separately from or in combination with the polycrystalline silicon region.

Techniques for fabricating a memory device which has reduced neighboring word line interference, and a corresponding memory device. The memory device comprises a stack of alternating conductive and dielectric layers, where the conductive layers form word lines or control gates of memory cells. In one aspect, rounding off of the control gate layers due to inadvertent oxidation during fabrication is avoided. An amorphous silicon layer is deposited along the sidewall of the memory holes, adjacent to the control gate layers. Si.sub.3N.sub.4 is deposited along the amorphous silicon layer and oxidized in the memory hole to form SiO.sub.2. The amorphous silicon layer acts as an oxidation barrier for the sacrificial material of the control gate layers. The amorphous silicon layer is subsequently oxidized to also form SiO.sub.2. The two SiO.sub.2 layers together form a blocking oxide layer.

A method for preparing silicon substrate having average crystallite size greater than or equal to 20 μm, including at least the steps of: (i) providing polycrystalline silicon substrate of which average grain size is less than or equal to 10 μm; (ii) subjecting substrate to overall homogeneous plastic deformation, at temperature of at least 1000° C.; (iii) subjecting substrate to localized plastic deformation in plurality of areas of substrate, called external stress areas, spacing between two consecutive areas being at least 20 μm, local deformation of substrate being strictly greater than overall deformation carried out in step (ii); step (iii) being able to be carried out subsequent to or simultaneous to step (ii); and (iv) subjecting substrate obtained in step (iii) to recrystallization heat treatment in solid phase, at temperature strictly greater than temperature used in step (ii), in order to obtain desired substrate.

A method for manufacturing a semiconductor device is provided. The method includes forming at least one epitaxial layer over a substrate; forming a mask over the epitaxial layer; patterning the epitaxial layer into a semiconductor fin; depositing a semiconductor capping layer over the semiconductor fin and the mask, wherein the semiconductor capping layer has a first portion that is amorphous on a sidewall of the mask; performing a thermal treatment such that the first portion of the semiconductor capping layer is converted from amorphous into crystalline; forming an isolation structure around the semiconductor fin; and forming a gate structure over the semiconductor fin.

A method of manufacturing a semiconductor device includes: loading a substrate into a process container after dry-etching a portion of a silicon film formed in a recess on the substrate; performing etching to partially or entirely remove the silicon film remaining on a side wall inside the recess by supplying an etching gas selected from a hydrogen bromide gas and a hydrogen iodide gas into the process container of a vacuum atmosphere while heating the substrate; subsequently forming a silicon film inside the recess; and heating the substrate to increase a grain size of the silicon film.

A semiconductor integrated circuit device may include a structure, a first capping layer, a channel layer and a second capping layer. The structure may have an opening formed in the structure. The first capping layer may be formed in the opening of the structure. The channel layer may be arranged between the structure and the first capping layer. The second capping layer may be arranged on the channel layer and the first capping layer.