A method for producing a nitride semiconductor stacked body includes: a first nitride semiconductor layer forming step of forming a first nitride semiconductor layer above a substrate within a reaction furnace; a second nitride semiconductor layer forming step of forming a second nitride semiconductor layer above the first nitride semiconductor layer; and a third nitride semiconductor layer forming step of forming a third nitride semiconductor layer on the upper surface of the second nitride semiconductor layer, the third nitride semiconductor layer having a band gap larger than the band gap of the second nitride semiconductor layer. No interval is provided between the second nitride semiconductor layer forming step and the third nitride semiconductor layer forming step, and the third nitride semiconductor layer forming step is performed continuously after the second nitride semiconductor layer forming step.

A method for forming SiGe-based regions with different Ge concentrations is provided. After defining the regions 1, 2 on a SOI substrate, a grating of masking patterns is formed on at least one region 2. After the epitaxial growth of a Ge-based layer in each of the regions, a first vertical diffusion is carried out. A second horizontal diffusion is then carried out such that the Ge diffuses beneath the masking patterns of the region 2. Thus, the region 2 has a Ge concentration that is lower than the Ge concentration of the region 1.

A novel and useful quantum computing machine architecture that includes a classic computing core as well as a quantum computing core. A programmable pattern generator executes sequences of instructions that control the quantum core. In accordance with the sequences, a pulse generator functions to generate the control signals that are input to the quantum core to perform quantum operations. A partial readout of the quantum state in the quantum core is generated that is subsequently re-injected back into the quantum core to extend decoherence time. Access gates control movement of quantum particles in the quantum core. Errors are corrected from the partial readout before being re-injected back into the quantum core. Internal and external calibration loops calculate error syndromes and calibrate the control pulses input to the quantum core. Control of the quantum core is provided from an external support unit via the pattern generator or can be retrieved from classic memory where sequences of commands for the quantum core are stored a priori in the memory. A cryostat unit functions to provide several temperatures to the quantum machine including a temperature to cool the quantum computing core to approximately 4 Kelvin.

Semiconductor devices including structures of active region are disclosed. An example semiconductor device according to the disclosure includes a substrate, a layer on the substrate and a dielectric layer on the layer. The layer includes an interface in contact with the dielectric layer. The interface includes a first portion on a surface of the layer and a second portion perpendicular to the first portion.

Embodiments relate to a layered material (having a substrate, at least a buffer layer, with zero or more growth layers) that has been intercalated via a process that decouples (physically and electronically) the buffer layer from the substrate, thereby resulting in the creation of few-atom thick metal layers that exhibit a range of optical properties, including plasmonic or electronic resonance, that enables superior optical (e.g. Raman) detection of molecules.

Embodiments disclosed herein relate to using an implantation process and a melting anneal process performed on a nanosecond scale to achieve a high surface concentration (surface pile up) dopant profile and a retrograde dopant profile simultaneously. In an embodiment, a method includes forming a source/drain structure in an active area on a substrate, the source/drain structure including a first region comprising germanium, implanting a first dopant into the first region of the source/drain structure to form an amorphous region in at least the first region of the source/drain structure, implanting a second dopant into the amorphous region containing the first dopant, and heating the source/drain structure to liquidize and convert at least the amorphous region into a crystalline region, the crystalline region containing the first dopant and the second dopant.

A group III-nitride (III-N)-based electronic device includes an engineered substrate, a metalorganic chemical vapor deposition (MOCVD) III-N-based epitaxial layer coupled to the engineered substrate, and a hybrid vapor phase epitaxy (HVPE) III-N-based epitaxial layer coupled to the MOCVD epitaxial layer.

In one embodiment, a method of manufacturing a semiconductor device includes forming a first semiconductor layer including impurity atoms with a first density, on a first substrate, forming a second semiconductor layer including impurity atoms with a second density higher than the first density, on the first semiconductor layer, and forming a porous layer resulting from porosification of at least a portion of the second semiconductor layer. The method further includes forming a first film including a device, on the porous layer, providing a second substrate provided with a second film including a device, and bonding the first and second substrates to sandwich the first and second films. The method further includes separating the first and second substrates from each other such that a first portion of the porous layer remains on the first substrate and a second portion of the porous layer remains on the second substrate.

The invention is a special designed pattern heterogeneous substrate, which is epitaxially deposited on a heterogeneous substrate by two step growth, and a thermal cycle annealing is added to reduce the lattice mismatch between the layers and the difference in thermal expansion coefficient, thereby obtaining a better stress. The quality of the semiconductor epitaxial layer is improved, and the present invention can easily grasp the timing of stress release when the semiconductor is grown on the heterogeneous substrate, avoid cracks in the semiconductor epitaxial layer, and form a crack free zone in the middle of the semiconductor epitaxial layer.

A semiconductor device includes a gate structure disposed over a channel region, a source/drain epitaxial layer disposed at a source/drain region, a nitrogen containing layer disposed on the source/drain epitaxial layer, a silicide layer disposed on the nitrogen containing layer, and a conductive contact disposed on the silicide layer.