A semiconductor body having first and second vertically spaced apart surfaces is formed. A gate trench that vertically extends from the first surface of the semiconductor body towards the second surface is formed. A gate electrode and a gate dielectric are formed in the gate trench. The gate dielectric electrically insulates the gate electrode from adjacent semiconductor material. A doped superjunction region vertically extending from a bottom of the gate trench towards the second surface of the semiconductor body is formed. The doped superjunction region includes first, second, and third doped pillars vertically extending from the first surface of the first semiconductor layer and directly adjoining one another. The second pillar is laterally centered between the first and third pillars and has an opposite conductivity type as the first and third pillars.

A silicon carbide semiconductor device includes a drift layer of a first conductivity type, a source region of the first conductivity type, an active trench formed in penetration through the source region, a base region, a termination trench formed around the active trench, a gate insulating film formed on a bottom surface, a side surface of the active trench, a gate electrode embedded and formed in the active trench with the gate insulating film interposed therebetween, a protective diffusion layer of a second conductivity type formed in a lower portion of the active trench and a part of a lower portion of the termination trench and having a first impurity concentration, and a termination diffusion layer of the second conductivity type formed on an outside of the protective diffusion layer in the lower portion of the termination trench and having a second impurity concentration lower than the first impurity concentration.

A power semiconductor device includes semiconductor layer structure comprising a semiconductor drift region of a first conductivity type and an edge termination region comprising a plurality of guard rings of a second conductivity type. The guard rings extend into a surface of the semiconductor drift region. The guard rings respectively comprise a first portion adjacent the surface and a second portion spaced from the surface, where the first portion is wider than the second portion. Related devices and fabrication methods are also discussed.

A semiconductor device includes a p-type semiconductor region in contact with a bottom face of a trench gate, wherein the p-type semiconductor region includes a first p-type semiconductor region containing a first type of p-type impurities and a second p-type semiconductor region containing a second type of p-type impurities. The first p-type semiconductor region is located between the trench gate and the second p-type semiconductor region. In a view along the depth direction, the second p-type semiconductor region is located within a part of the first p-type semiconductor region. A diffusion coefficient of the second type of p-type impurities is smaller than a diffusion coefficient of the first type of p-type impurities.

The steps of preparing a silicon carbide layer having a main surface, forming on the main surface, a first mask layer located on a first region to be a channel region and having a first opening portion on each of opposing regions with the first region lying therebetween, and forming a high-concentration impurity region having a first conductivity type and being higher in impurity concentration than the silicon carbide layer in a region exposed through the first opening portion, by implanting ions into the main surface with the first mask layer being interposed are included.

Disclosed herein are methods for increasing MOSFET threshold voltage to enable higher SiC mobility. In some embodiments, a method includes providing a device structure including a dielectric layer over an epitaxial layer, patterning a hardmask layer over the dielectric layer, performing a first ion implant to form a well in the epitaxial layer, and performing a second ion implant to form an interface layer between the well and the dielectric layer.

The subject matter disclosed herein relates to semiconductor power devices, such as silicon carbide (SiC) power devices. In particular, the subject matter disclosed herein relates to shielding regions in the form of body region extensions for that reduce the electric field present between the well regions of neighboring device cells of a semiconductor device under reverse bias. The disclosed body region extensions have the same conductivity-type as the body region and extend outwardly from the body region and into the JFET region of a first device cell such that a distance between the body region extension and a region of a neighboring device cell having the same conductivity type is less than or equal to the parallel JFET width. The disclosed shielding regions enable superior performance relative to a conventional stripe device of comparable dimensions, while still providing similar reliability (e.g., long-term, high-temperature stability at reverse bias).

A semiconductor body having first and second vertically spaced apart surfaces is formed. A gate trench that vertically extends from the first surface of the semiconductor body towards the second surface is formed. A gate electrode and a gate dielectric are formed in the gate trench. The gate dielectric electrically insulates the gate electrode from adjacent semiconductor material. A doped superjunction region vertically extending from a bottom of the gate trench towards the second surface of the semiconductor body is formed. The doped superjunction region includes first, second, and third doped pillars vertically extending from the first surface of the first semiconductor layer and directly adjoining one another. The second pillar is laterally centered between the first and third pillars and has an opposite conductivity type as the first and third pillars.

A method of making a silicon carbide MOSFET device can include: providing a substrate with a first doping type; forming a patterned first barrier layer on a first surface of the substrate; forming a source region with a first doping type in the substrate; forming a base region with a second doping type and a contact region with a second doping type in the substrate, and forming a gate structure. The first barrier layer can include a first portion and a second portion, the first portion can include a semiconductor layer and a removable layer different from the semiconductor layer, and the second portion can only include the removable layer.

A silicon carbide semiconductor device includes a silicon carbide layer and a gate insulating layer. The silicon carbide layer has a main surface. The gate insulating layer is arranged as being in contact with the main surface of the silicon carbide layer. The silicon carbide layer includes a drift region having a first conductivity type, a body region having a second conductivity type different from the first conductivity type and being in contact with the drift region, a source region having the first conductivity type and arranged as being spaced apart from the drift region by the body region, and a protruding region arranged to protrude from at least one side of the source region and the drift region into the body region, being in contact with the gate insulating layer, and having the first conductivity type.