An epitaxy substrate and a method of manufacturing the same are provided. The epitaxy substrate includes a device substrate and a handle substrate. The device substrate has a first surface and a second surface opposite to each other, and a bevel disposed between the first and the second surfaces. The handle substrate is bonded to the second surface of the device substrate, wherein the oxygen content of the device substrate is less than the oxygen content of the handle substrate, and a bonding angle greater than 90° is between the bevel of the device substrate and the handle substrate.

Embodiments of semiconductor devices and fabrication methods thereof are disclosed. In an example, a semiconductor device includes a first semiconductor structure including a processor and a first bonding layer including a plurality of first bonding contacts. The semiconductor device also includes a second semiconductor structure including an array of static random-access memory (SRAM) cells and a second bonding layer including a plurality of second bonding contacts. The semiconductor device further includes a bonding interface between the first bonding layer and the second bonding layer. The first bonding contacts are in contact with the second bonding contacts at the bonding interface.

A method of manufacturing a semiconductor device includes the following steps. A device wafer having a product-obtaining part and an edge part surrounding the product-obtaining part is provided. A passivation layer is formed to cover the device wafer. A first oxide cap layer is formed to cover the passivation layer. An edge trimming process is performed to polish an edge part of the first oxide cap layer, an edge part of the passivation layer and the edge part of the device wafer. A removing process is performed to remove the first oxide cap layer after the edge trimming process is performed. A second oxide cap layer is formed to cover the first oxide cap layer and the edge part of the device wafer.

The present invention provides a method for preparing a gallium oxide semiconductor structure and a gallium oxide semiconductor structure obtained thereby. The method comprises: providing a gallium oxide single-crystal wafer (1) having an implantation surface (1a) (S1); performing an ion implantation from the implantation surface (1a) into the gallium oxide single-crystal wafer (1), such that implanted ions reach a preset depth and an implantation defect layer (11) is formed at the preset depth (S2); bonding the implantation surface (1a) to a high thermal conductivity substrate (2) to obtain a first composite structure (S3); performing an annealing treatment on the first composite structure such that the gallium oxide single-crystal wafer (1) in the first composite structure is peeled off along the implantation defect layer (11), thereby obtaining a second composite structure and a third composite structure (S4); and performing a surface treatment on the second composite structure to remove a first damaged layer (111), so as to obtain a gallium oxide semiconductor structure comprising a first gallium oxide layer (12) and the high thermal conductivity substrate (2) (S5). In the gallium oxide semiconductor structure formed using the above method, the first gallium oxide layer (12) is integrated with the high thermal conductivity substrate (2) to effectively improve the thermal conductivity of the first gallium oxide layer (12).

Embodiments of the present disclosure describe techniques for reducing in-plane distortion from wafer to wafer bonding using a dummy wafer. One embodiment is an apparatus formed using a dummy wafer, the apparatus comprising: a device layer fusion bonded to a first side of a carrier wafer, wherein the dummy wafer comprises a first wafer and the carrier wafer comprises a second wafer that is different than the first wafer; wherein the device layer comprise a portion of a third wafer that is different than the second wafer; and wherein a second opposite side of the carrier wafer includes: a removal process artifact, wherein a distortion signature present in the portion of the second wafer is indicative of the use of the dummy wafer fusion bonded to the second side of the carrier wafer, or a remainder of the dummy wafer. Other embodiments may be disclosed and/or claimed.

The present disclosure describes a method that includes forming a first two-dimensional (2D) layer on a first substrate and attaching a second 2D layer to a carrier film. The method also includes bonding the second 2D layer to the first 2D layer to form a heterostack including the first and second 2D layers. The method further includes separating the first 2D layer of the heterostack from the first substrate and attaching the heterostack to a second substrate. The method further includes removing the carrier film from the second 2D layer.

Methods for obtaining a free-standing thick (>5 μm) epitaxial material layer or heterostructure stack and for transferring the thick epitaxial layer or stack to an arbitrary substrate. A thick epitaxial layer or heterostructure stack is formed on an engineered substrate, with a sacrificial layer disposed between the epitaxial layer and the engineered substrate. When the sacrificial layer is removed, the epitaxial layer becomes a thick freestanding layer that can be transferred to an arbitrary substrate, with the remaining engineered substrate being reusable for subsequent material layer growth. In an exemplary case, the material layer is a GaN layer and can be selectively bonded to an arbitrary substrate to selectively produce a Ga-polar or an N-polar GaN layer.

Embodiments of semiconductor devices and fabrication methods thereof are disclosed. In an example, a semiconductor device includes a first semiconductor structure including a processor, an array of static random-access memory (SRAM) cells, and a first bonding layer including a plurality of first bonding contacts. The semiconductor device also includes a second semiconductor structure including an array of NAND memory cells and a second bonding layer including a plurality of second bonding contacts. The semiconductor device further includes a bonding interface between the first bonding layer and the second bonding layer. The first bonding contacts are in contact with the second bonding contacts at the bonding interface.

A method of wafer bonding includes: forming a first hole in a first insulation layer disposed over a first substrate; performing a first deposition-self-etch process to deposit a first conductive material in the first hole to form a first conductive plug; forming a second hole in a second insulation layer disposed over a second substrate; performing a second deposition-self-etch process to deposit a second conductive material in the second hole to form a second conductive plug; and bonding the first conductive plug with the second conductive plug to form a first grain fusion layer between the first conductive plug and the second conductive plug.

Provided are a device substrate with high thermal conductivity, with high heat dissipation, and with a small loss at high frequencies, and a method of manufacturing the device substrate. A device substrate 1 of the present invention can be manufactured by: provisionally bonding a Si device layer side of an SOI device substrate 10 to a support substrate 20 using a provisional bonding adhesive 31, the SOI device substrate including a Si base substrate 11, a buried layer 12 formed on the Si base substrate, having high thermal conductivity, and being an electrical insulator, and a Si device layer 13 formed on the buried layer; removing the Si base substrate 11 of the provisionally bonded SOI device substrate until the buried layer is exposed, thereby obtaining a thinned device wafer 10a; transfer-bonding the buried layer side of the thinned device wafer and a transfer substrate 40 to each other using a transfer adhesive 32 having a heat-resistant temperature of at least 150° C. by applying heat and pressure, the transfer substrate having high thermal conductivity and being an electrical insulator; and separating the support substrate 20.