A cost effective process flow for manufacturing semiconductor on insulator structures is parallel is provided. Each of the multiple semiconductor-on-insulator composite structures prepared in parallel comprises a charge trapping layer (CTL).

When III-V semiconductor material is bonded to an oxide material, water molecules can degrade the bonding if they become trapped at the interface between the III-V material and the oxide material. Because water molecules can diffuse readily through oxide material, and may not diffuse as readily through III-V material or through silicon, forcing the III-V material against the oxide material can force water molecules at the interface into the oxide material and away from the interface. Water molecules present at the interface can be forced during manufacturing through vertical channels in a silicon layer into a buried oxide layer thereby to enhance bonding between the III-V material and the oxide material. Water molecules can be also forced through lateral channels in the oxide material, past a periphery of the III-V material, and, through diffusion, out of the oxide material into the atmosphere.

A cost effective process flow for manufacturing semiconductor on insulator structures is parallel is provided. Each of the multiple semiconductor-on-insulator composite structures prepared in parallel includes a charge trapping layer (CTL).

The present disclosure provides a method for cleaning a bonding interface before bonding. The method includes: providing a first surface and a second surface for bonding, the first surface being a non-crystal surface and the second surface being a crystal surface; and cleaning the first surface and the second surface with ammonia respectively before bonding, wherein at least one of parameters of an ammonia concentration and a cleaning temperature for cleaning the first surface is higher than a counterpart of parameters for cleaning the second surface.

Methods of forming semiconductor structures include providing a polymeric material over a carrier substrate, bonding another substrate to the polymeric material, and lowering a temperature of the polymeric material to below about 15 C. to separate the another substrate from the carrier substrate. Some methods include forming a polymeric material over a first substrate, securing a second substrate to the first substrate over the polymeric material, cooling the polymeric material to a temperature below a glass transition temperature of the polymeric material, and separating the second substrate from the first substrate. Semiconductor structures may include a polymeric material over at least a portion of a first substrate, an adhesive material over the polymeric material, and a second substrate over the adhesive material. The polymeric material may have a glass transition temperature of about 10 C. or lower and a melting point of about 100 C. or greater.

A semiconductor device manufacturing method according to the present disclosure includes: preparing a substrate having a surface layer at least made of semiconductor; forming a mask pattern having a plurality of openings on the surface layer using materials free of semiconductor vapor-phase growth; forming a brittle portion in each opening by a vapor-phase growth process; forming crystal growth-derived layer on the mask pattern by a vapor-phase growth process by growth of semiconductor crystals on a surface of the brittle portion ; and separating, at brittle portion, a crystal growth-derived layer from substrate.

Methods of fabricating semiconductor device packages may involve forming trenches in a first wafer. A dielectric material may be placed over a first active surface. Electrically conductive elements may be operatively connected to bond pads of a second wafer with the dielectric material interposed between the first wafer and the second wafer. Force may be applied to the first wafer and the second wafer while exposing the first wafer and the second wafer to an elevated temperature. Portions of the dielectric material may flow into the trenches. The elevated temperature may be reduced to at least partially solidify the dielectric material. A thickness of the first wafer may be reduced to reveal the portions of the dielectric material in the trenches. The first wager may be singulated and the second wafer may be singulated to form semiconductor dice.

A semiconductor structure with a high resistivity wafer includes a device wafer. The device wafer includes a front side and a back side. A semiconductor element is disposed on the front side. An interlayer dielectric covers the front side. A high resistivity wafer consists of an insulating material. A dielectric layer encapsulates the high resistivity wafer. The dielectric layer contacts the interlayer dielectric.

Capacitive coupling of integrated circuit die components and other conductive areas is provided. Each component to be coupled has a surface that includes at least one conductive area, such as a metal pad or plate. An ultrathin layer of dielectric is formed on at least one surface to be coupled. When the two components, e.g., one from each die, are permanently contacted together, the ultrathin layer of dielectric remains between the two surfaces, forming a capacitor or capacitive interface between the conductive areas of each respective component. The ultrathin layer of dielectric may be composed of multiple layers of various dielectrics, but in one implementation, the overall thickness is less than approximately 50 nanometers. The capacitance per unit area of the capacitive interface formed depends on the particular dielectric constants of the dielectric materials employed in the ultrathin layer and their respective thicknesses. Electrical and grounding connections can be made at the edge of the coupled stack.

Disclosed herein is an X-ray detector comprises: an X-ray absorption layer configured to absorb X-ray photons; an electronics layer comprising an electronics system configured to process or interpret signals generated by the X-ray photons incident on the X-ray absorption layer; and a temperature driver in the X-ray absorption layer or the electronics layer.