A substrate includes a polycrystalline ceramic core; a first adhesion layer encapsulating the polycrystalline ceramic core; a conductive layer encapsulating the first adhesion layer; a second adhesion layer encapsulating the conductive layer; a barrier layer encapsulating the second adhesion layer, and a bonding layer coupled to the barrier layer, and a substantially single crystalline silicon layer coupled to the bonding layer.

A method of transferring a device layer in a SOI wafer obtained by stacking a Si layer, an insulator layer, and the device layer to a transfer substrate, includes a step of temporarily bonding a surface on which the device layer is formed of the SOI wafer to a supporting substrate using an adhesive for temporary bonding, a step of removing the Si layer of the SOI wafer until the insulator layer is exposed and obtaining a thinned device wafer, a step of coating only the transfer substrate with an adhesive for transfer and then bonding the insulator layer in the thinned device wafer to the transfer substrate via the adhesive for transfer, a step of thermally curing the adhesive for transfer under a load at the same time as or after bonding, a step of peeling off the supporting substrate, and a step of removing the adhesive.

Embodiments of semiconductor structures for wafer flatness control and methods for using and forming the same are disclosed. In an example, a model indicative of a flatness difference of a wafer between a first direction and a second direction is obtained. The flatness difference is associated with one of a plurality of fabrication stages of a plurality of semiconductor devices on a front side of the wafer. A compensation pattern is determined for reducing the flatness difference based on the model. At the one of the plurality of the fabrication stages, a compensation structure is formed on a backside opposite to the front side of the wafer based on the compensation pattern to reduce the flatness difference.

A method for manufacturing a bonded SOI wafer, including depositing a polycrystalline silicon layer on a base wafer, forming an insulator film on a bond wafer, bonding the bond wafer and a polished surface of the silicon layer with the insulator film interposed, and thinning the bond wafer, wherein a silicon single crystal wafer having a resistivity of 100 .Math.cm or more is the base wafer, the step of depositing the silicon layer includes a stage of forming an oxide film on the surface of the base wafer, and the silicon layer is deposited between 1050 C. and 1200 C. Accordingly, the method enables a polycrystalline silicon layer to be deposited while preventing the progress of single crystallization even through a heat treatment step in the SOI wafer manufacturing process or a heat treatment step in the device manufacturing process and can improve throughput in the polycrystalline silicon layer depositing step.

A semi-finished product having a substrate with a first side and an opposite second side is provided, wherein at least one diamond layer is arranged on the first side, wherein the diamond layer comprises monocrystalline diamond and the substrate comprises a material different from the diamond layer. A method for producing such a semi-finished product is provided and an integrated optical component may be produced from the semi-finished product.

A method of fabricating a ceramic substrate structure includes providing a ceramic substrate, encapsulating the ceramic substrate in a barrier layer, and forming a bonding layer coupled to the barrier layer. The method further includes removing a portion of the bonding layer to expose at least a portion of the barrier layer and define fill regions, and depositing a second bonding layer on the at least a portion of the exposed barrier layer and the fill regions.

A three-dimensional (3D) bonded semiconductor structure is provided in which a first bonding oxide layer of a first semiconductor structure is bonded to a second bonding oxide layer of a second semiconductor structure. Each of the first and second bonding oxide layers has a metallic bonding structure embedded therein, wherein each metallic bonding structure contains a columnar grain microstructure. Furthermore, at least one columnar grain extends across a bonding interface that is present between the metallic bonding structures. The presence of the columnar grain microstructure in the metallic bonding structures, together with at least one columnar grain microstructure extending across the bonding interface between the two bonded metallic bonding structures, can provide a 3D bonded structure having mechanical bonding strength and electrical performance enhancements.

According to an embodiment, a sensor package includes an electrically insulating substrate including a cavity in the electrically insulating substrate, an ambient sensor, an integrated circuit die embedded in the electrically insulating substrate, and a plurality of conductive interconnect structures coupling the ambient sensor to the integrated circuit die. The ambient sensor is supported by the electrically insulating substrate and arranged adjacent the cavity.

An apparatus and method is provided for controlling a propagation of a bond wave during semiconductor processing. The apparatus has a first chuck to selectively retain a first workpiece. A second chuck selectively retains a second workpiece. The first and second chucks selectively secure at least a periphery of the respective first workpiece and second workpiece. An air vacuum is circumferentially located in a region between the first chuck and second chuck. The air vacuum is configured to induce a vacuum between the first workpiece and second workpiece to selectively bring the first workpiece and second workpiece together from a propagation point. The air vacuum can be localized air vacuum guns, a vacuum disk, or an air curtain positioned about the periphery of the region between the first chuck and second chuck. The air curtain induces a lower pressure within the region between the first and second chucks.

A method for adjusting the stress state of a piezoelectric film having a first stress state at room temperature includes a step of forming an assembly including a carrier having a thermal expansion coefficient, a compliant layer placed on the carrier, and the piezoelectric film placed on the compliant layer, the piezoelectric film having a thermal expansion coefficient different from that of the carrier. The method also includes a step of heat treating the assembly, in which the assembly is heated to a treatment temperature above the glass transition temperature of the compliant layer. The present disclosure also relates to a process for fabricating an acoustic wave device comprising the piezoelectric layer the stress state of which was adjusted as described herein.