A method of fabricating a semiconductor device is provided. A hybrid bonded structure is provided. A cover lid comprising a base portion and at least one dummy portion protruding from the base portion is provided. The at least one dummy portion of the cover lid is bonded to the hybrid bonding structure. The base portion is removed. A redistribution structure over the hybrid bonding structure and the at least one dummy portion is formed.

A method for manufacturing a semiconductor device includes: forming a release layer including a first polycrystalline semiconductor layer provided on a first substrate, and a second polycrystalline semiconductor layer provided between the first substrate and the first polycrystalline semiconductor layer and having a p-type impurity concentration which is lower than that of the first polycrystalline semiconductor layer, and an n-type impurity concentration which is higher than that of the first polycrystalline semiconductor layer; subjecting the first polycrystalline semiconductor layer to anodic chemical conversion to form a first porous layer; forming a first device layer on the first porous layer; and bonding together the first device layer and a second device layer provided on a second substrate.

A semiconductor device includes a semiconductor layer with opposing first and second main surfaces and a first column extending from the first main surface and having a first concentration of a dopant of the first conductivity type. A trench with a sidewall and bottom extends at least partially through the semiconductor layer from the first main surface. A second column between the trench sidewall and the first column has a second concentration of a dopant of a second conductivity type and is formed in the semiconductor layer and extends from the first main surface. A trench oxide layer is in contact with at least the trench sidewall and the trench bottom. A trench nitride layer covers the trench oxide layer at least on the trench sidewall. A dielectric seal material seals the trench proximate the first main surface of the semiconductor layer such that the trench is air-tight.

In an embodiment, a device includes: a first device including: an integrated circuit device having a first connector; a first photosensitive adhesive layer on the integrated circuit device; and a first conductive layer on the first connector, the first photosensitive adhesive layer surrounding the first conductive layer; a second device including: an interposer having a second connector; a second photosensitive adhesive layer on the interposer, the second photosensitive adhesive layer physically connected to the first photosensitive adhesive layer; and a second conductive layer on the second connector, the second photosensitive adhesive layer surrounding the second conductive layer; and a conductive connector bonding the first and second conductive layers, the conductive connector surrounded by an air gap.

A device includes a device level having a metallization structure coupled to a semiconductor device and a transistor above the device level. The transistor has a body including a single crystal group III-V or group IV semiconductor material, a source structure on a first portion of the body and a drain structure on a second portion of the body, where the source structure is separate from the drain structure. The transistor further includes a gate structure including a first gate structure portion in a recess in the body and a second gate structure portion between the source structure and the drain structure. A source contact is coupled with the source structure and a drain contact is coupled with the drain structure. The source contact is in contact with the metallization structure in the device level.

A method of forming a microelectronic device comprises forming a microelectronic device structure comprising memory cells, digit lines, word lines, and at least one isolation material covering and surrounding the memory cells, the digit lines, and the word lines. An additional microelectronic device structure comprising control logic devices and at least one additional isolation material covering and surrounding the control logic devices is formed. The additional microelectronic device structure is attached to the microelectronic device structure. Contact structures are formed to extend through the at least one isolation material and the at least one additional isolation material. Some of the contact structures are coupled to some of the digit lines and some of the control logic devices. Some other of the contact structures are coupled to some of the word lines and some other of the control logic devices. Microelectronic devices, electronic systems, and additional methods are also described.

An integrated device, the device including: a first level including a first mono-crystal layer, the first mono-crystal layer including a plurality of single crystal transistors; an overlying oxide disposed on top of the first level; a second level including a second mono-crystal layer, the second level overlaying the oxide, where the second mono-crystal layer includes a plurality of image sensors, where the second level is bonded to the first level with an oxide to oxide bond; a plurality of pixel control circuits; a plurality of memory circuits; and a third level disposed underneath the first level, where the third level includes a plurality of third transistors.

A bonded object production method according to an embodiment uses a continuous furnace to process a stacked body including a metal member, a ceramic member, and a brazing material layer located therebetween, while conveying the stacked body; and the method includes a process of heating the stacked body in an inert atmosphere from 200? C. to a bonding temperature at an average temperature raising rate of the stacked body of not less than 15? C./min, a process of bonding the stacked body in an inert atmosphere at the bonding temperature that is within a range of not less than 600? C. and not more than 950? C., and a process of cooling the stacked body from the bonding temperature to 200? C. at an average temperature lowering rate of the stacked body of not less than 15? C./min. A ceramic substrate is favorably a silicon nitride substrate.

A bulk acoustic wave resonator and a method of manufacturing the same are provided. The bulk acoustic wave resonator includes: a first carrier substrate; a barrier layer on a main surface of the first carrier substrate and configured to prevent an undesired conductive channel from being generated due to charge accumulation on the main surface; a buffer layer on a side of the barrier layer away from the first carrier substrate; a piezoelectric layer on a side of the buffer layer away from the barrier layer; a first electrode and a second electrode on opposite sides of the piezoelectric layer; a first passivation layer and a second passivation layer, respectively covering sidewalls of the first electrode and the second electrode; a dielectric layer between the first passivation layer and the buffer layer, wherein a first cavity is provided between the first passivation layer and the dielectric layer.

A bonding method for bonding two substrates (W1, W2) includes: a heat treatment process of heating a bonding surface to be bonded to each other of each of the two substrates (W1, W2) to a temperature higher than 60 C. in a reduced-pressure atmosphere; an activation treatment process of activating the bonding surface of each of the two substrates (W1, W2) in a state of maintaining the reduced-pressure atmosphere after the heat treatment process; and a bonding process of bonding the two substrates (W1, W2) in a state of maintaining the reduced-pressure atmosphere after the activation treatment process. In the heat treatment process, the state of heating the bonding surface of each of the two substrates (W1, W2) to a temperature higher than 60 C. may be maintained for 30 seconds or more in a state of maintaining the reduced-pressure atmosphere. The gas pressure in the heat treatment process may be 10.sup.2 Pa or less.