A 3DIC structure includes a die, a conductive terminal, and a dielectric structure. The die is bonded to a carrier through a bonding film. The conductive terminal is disposed over and electrically connected to the die. The dielectric structure comprises a first dielectric layer and a second dielectric layer. The first dielectric layer is disposed laterally aside the die. The second dielectric layer is disposed between the first dielectric layer and the bonding film, and between the die and the boding film. A second edge of the second dielectric layer is more flat than a first edge of the first dielectric layer.

A method of manufacturing a composite structure comprises: a) providing a donor substrate of a single-crystal semiconductor material, b) implanting ions into the donor substrate, excluding an annular peripheral region, to form a buried brittle plane, the implantation conditions defining a first thermal budget for obtaining bubbling on a face of the donor substrate and a second thermal budget for obtaining a fracture in the brittle plane, c) forming a stiffening film on the donor substrate, carried out by applying a thermal budget lower than the first thermal budget, the stiffening film being perforated in the form of a mesh, the perforated stiffening film leaving a plurality of zones of the front face bare, d) depositing a carrier substrate on the donor substrate carried out by applying a thermal budget greater than the first thermal budget, and e) separating the donor substrate along the brittle plane.

This method comprises the steps of: a) forming a set of first trenches on the first surface of the wafer; b) forming a set of second trenches on the second surface of the wafer, at least partially facing the first trenches; c) filling the first trenches with a first material having a CTE .sub.1; d) filling the second trenches with a second material having a CTE .sub.2, and verifying .sub.2>.sub.0 or .sub.2<.sub.0 depending on whether the first material verifies .sub.1>.sub.0 or .sub.1<.sub.0.

A 3DIC structure includes a die, a conductive terminal, and a dielectric structure. The die is bonded to a carrier through a bonding film. The conductive terminal is disposed over and electrically connected to the die. The dielectric structure comprises a first dielectric layer and a second dielectric layer. The first dielectric layer is disposed laterally aside the die. The second dielectric layer is disposed between the first dielectric layer and the bonding film, and between the die and the boding film. A second edge of the second dielectric layer is more flat than a first edge of the first dielectric layer.

A device includes a device level having a metallization structure coupled to a semiconductor device and a transistor above the device level. The transistor has a body including a single crystal group III-V or group IV semiconductor material, a source structure on a first portion of the body and a drain structure on a second portion of the body, where the source structure is separate from the drain structure. The transistor further includes a gate structure including a first gate structure portion in a recess in the body and a second gate structure portion between the source structure and the drain structure. A source contact is coupled with the source structure and a drain contact is coupled with the drain structure. The source contact is in contact with the metallization structure in the device level.

A method for removing a portion of a crystalline material (e.g., SiC) substrate includes joining a surface of the substrate to a rigid carrier (e.g., >800 ?m thick), with a subsurface laser damage region provided within the substrate at a depth relative to the surface. Adhesive material having a glass transition temperature above 25? C. may bond the substrate to the carrier. The crystalline material is fractured along the subsurface laser damage region to produce a bonded assembly including the carrier and a portion of the crystalline material. Fracturing of the crystalline material may be promoted by (i) application of a mechanical force proximate to at least one carrier edge to impart a bending moment in the carrier; (ii) cooling the carrier when the carrier has a greater coefficient of thermal expansion than the crystalline material; and/or (iii) applying ultrasonic energy to the crystalline material.

A method and a corresponding device for bonding a first substrate with a second substrate at mutually facing contact faces of the substrates. The method includes holding of the first substrate to a first holding surface of a first holding device and holding of the second substrate to a second holding surface of a second holding device. A change in curvature of the contact face of the first substrate and/or a change in curvature of the contact face of the second substrate are controlled during the bonding.

The present invention provides a method for preparing a gallium oxide semiconductor structure and a gallium oxide semiconductor structure obtained thereby. The method comprises: providing a gallium oxide single-crystal wafer (1) having an implantation surface (1a) (S1); performing an ion implantation from the implantation surface (1a) into the gallium oxide single-crystal wafer (1), such that implanted ions reach a preset depth and an implantation defect layer (11) is formed at the preset depth (S2); bonding the implantation surface (1a) to a high thermal conductivity substrate (2) to obtain a first composite structure (S3); performing an annealing treatment on the first composite structure such that the gallium oxide single-crystal wafer (1) in the first composite structure is peeled off along the implantation defect layer (11), thereby obtaining a second composite structure and a third composite structure (S4); and performing a surface treatment on the second composite structure to remove a first damaged layer (111), so as to obtain a gallium oxide semiconductor structure comprising a first gallium oxide layer (12) and the high thermal conductivity substrate (2) (S5). In the gallium oxide semiconductor structure formed using the above method, the first gallium oxide layer (12) is integrated with the high thermal conductivity substrate (2) to effectively improve the thermal conductivity of the first gallium oxide layer (12).

Methods for forming a semiconductor device are disclosed. According to some aspects, a first implantation is performed on a first of a first semiconductor structure to form a buried stop layer in the first substrate. A second semiconductor device is formed. The first semiconductor structure and the second semiconductor device are bonded. The first substrate is thinned and the buried stop layer is removed, and an interconnect layer is formed above the thinned first substrate.

A semiconductor device including: a plurality of transistors, where at least one of the transistors includes a first single crystal source, channel, and drain, where at least one of the transistors includes a second single crystal source, channel, and drain, where the second single crystal source, channel, and drain is disposed above the first single crystal source, channel, and drain, where at least one of the transistors includes a third single crystal source, channel, and drain, where the third single crystal source, channel, and drain is disposed above the second single crystal source, channel, and drain, where at least one of the transistors includes a fourth single crystal source, channel, and drain, where the fourth single crystal source, channel, and drain is disposed above the third single crystal source, channel, and drain, and where the fourth drain is aligned to the first drain with less than 40 nm misalignment.