A method for bonding a first substrate and a second substrate includes: forming a protrusion at a partial region of the first substrate; measuring a position of the first substrate after the protrusion is formed in the first substrate; and bonding the first substrate and the second substrate by contacting the protrusion of the first substrate with a surface of the second substrate to form a contact region and enlarging the contact region.

Small size chip handling and electronic component integration are accomplished using handle fixturing to transfer die or other electronic components from a full area array to a targeted array. Area array dicing of a thinned device wafer on a handle wafer/panel may be followed by selective or non-selective de-bonding of targeted die or electronic components from the handle wafer and optional attachment to a carrier such as a transfer head or tape. Alignment fiducials may facilitate precision alignment of the transfer head or tape to the device wafer and subsequently to the targeted array. Alternatively, the dies or other electronic elements are transferred selectively from either a carrier or the device wafer to the targeted array.

A foundry-agnostic post-processing method for a wafer is provided. The wafer includes an active surface, a substrate and an intermediate layer interposed between the active surface and the substrate. The method includes removing the wafer from an output yield of a wafer processing foundry, thinning the substrate to the intermediate layer or within microns of the intermediate layer to expose a new surface and bonding the new surface to an alternate material substrate which provides for enhanced device performance as compared to the substrate.

The exemplary embodiments describe techniques for a controlled chemical vapor deposition growth and transfer of arrayed TMD monolayers on predetermined locations, which enable the formation of single crystalline TMD monolayer arrays on specific locations. The unique growth process includes the patterning of transition metal oxide (e.g., MoO.sub.3) on the source substrate contacting the growth substrate face-to-face, where the growth of single crystalline TMD monolayers with controlled size and location, exclusively on predetermined locations on the growth substrates is accomplished. These TMD arrays can be align-transferred using a unique process that combines the wet and stamping transfer processes onto any target substrate with a pin-point accuracy, which dramatically enhances the integrity of transferred TMDs.

A semiconductor substrate structure and process for fabrication of the semiconductor substrate structure are described. The semiconductor substrate structure includes a silicon carbide (SiC) wafer substrate, an active gallium nitride (GaN) layer and a layer of microcrystalline diamond (MCD) layer disposed between the SiC wafer substrate and the GaN active layer. The MCD) layer is bonded to the SiC wafer substrate and to the GaN active layer.

A light emitting module including a mounting substrate, light emitting chips mounted on the mounting substrate, and pads, in which the light emitting chips include a first substrate, a first light emitting unit on a first surface of the first substrate, a second substrate spaced apart from the first substrate, and a second light emitting unit on a second surface of the second substrate, the first substrate includes a first side surface including a first modified surface, and the second substrate includes a second side surface facing the first side surface and including a second modified surface, the first modified surface includes first modified regions extended in a thickness direction and first ruptured regions disposed therebetween, the second modified surface includes second modified regions extended in the thickness direction and second ruptured regions disposed therebetween, and the first ruptured regions have the same width as the second ruptured regions.

A method of forming a microelectronic device comprises forming a microelectronic device structure comprising memory cells, digit lines, word lines, and at least one isolation material covering and surrounding the memory cells, the digit lines, and the word lines. An additional microelectronic device structure comprising control logic devices and at least one additional isolation material covering and surrounding the control logic devices is formed. The additional microelectronic device structure is attached to the microelectronic device structure. Contact structures are formed to extend through the at least one isolation material and the at least one additional isolation material. Some of the contact structures are coupled to some of the digit lines and some of the control logic devices. Some other of the contact structures are coupled to some of the word lines and some other of the control logic devices. Microelectronic devices, electronic systems, and additional methods are also described.

A metal-dielectric bonding method includes providing a first semiconductor structure including a first semiconductor layer, a first dielectric layer on the first semiconductor layer, and a first metal layer on the first dielectric layer, where the first metal layer has a metal bonding surface facing away from the first semiconductor layer; planarizing the metal bonding surface; applying a plasma treatment on the metal bonding surface; providing a second semiconductor structure including a second semiconductor layer, and a second dielectric layer on the second semiconductor layer, where the second dielectric layer has a dielectric bonding surface facing away from the second semiconductor layer; planarizing the dielectric bonding surface; applying a plasma treatment on the dielectric bonding surface; and bonding the first semiconductor structure with the second semiconductor structure by bonding the metal bonding surface with the dielectric bonding surface.

A 3DIC structure includes a die, a conductive terminal, and a dielectric structure. The die is bonded to a carrier through a bonding film. The conductive terminal is disposed over and electrically connected to the die. The dielectric structure comprises a first dielectric layer and a second dielectric layer. The first dielectric layer is disposed laterally aside the die. The second dielectric layer is disposed between the first dielectric layer and the bonding film, and between the die and the boding film. A second edge of the second dielectric layer is more flat than a first edge of the first dielectric layer.

Some embodiments include a method. The method can include: providing a carrier substrate; providing a first bond promoting layer over the carrier substrate; providing a second bond promoting layer over the carrier substrate; and depositing a first device substrate over the carrier substrate, the first bond promoting layer, and the second bond promoting layer. The first device substrate can be configured to bond to the carrier substrate with a first device substrate-carrier substrate adhesion strength. Meanwhile, depositing the first device substrate can include: bonding the first device substrate to the first bond promoting layer, the first device substrate bonding to the first bond promoting layer with a first device substrate-first bond promoting layer adhesion strength greater than the first device substrate-carrier substrate adhesion strength; and coupling the first device substrate to the carrier substrate. Other embodiments of related methods and devices are also disclosed.