A manufacturing method of a semiconductor device, in which a vacuum-pressure airtight chamber is defined by a space between a first substrate and a recessed portion of a second substrate, includes preparing the first substrate and the second substrate both of which contain silicon, joining the two substrates together, performing a heat treatment to emit hydrogen gas from the airtight chamber, and generating OH groups on the substrates before the joining. In the joining of the substrates together, the OH groups are bonded together to generate covalent bonds, and in the heat treatment, a part on which the OH groups are generated is heated at a temperature rise rate of 1 C./sec or smaller until a temperature of the substrate increases to 700 C. or higher, and a heating temperature and heating time are adjusted to emit hydrogen gas from the airtight chamber.

A system and method for clamping wafers together in alignment using pressure. The system and method involves holding a first wafer and a second wafer together in alignment using a wafer clamp within an ambient environment maintained at a first pressure and creating a second pressure at least partially around and between the first wafer and the second wafer held together by the wafer clamp, wherein the first pressure is greater than the second pressure. The first wafer and the second wafer are clamped together in alignment using a pneumatic force created by a pressure differential between the first pressure and the second pressure.

Direct-bonded native interconnects and active base dies are provided. In a microelectronic architecture, active dies or chiplets connect to an active base die via their core-level conductors. These native interconnects provide short data paths, which forgo the overhead of standard interfaces. The system saves redistribution routing as the native interconnects couple in place. The base die may contain custom logic, allowing the attached dies to provide stock functions. The architecture can connect diverse interconnect types and chiplets from various process nodes, operating at different voltages. The base die may have state elements for drive. Functional blocks aboard the base die receive native signals from diverse chiplets, and communicate with all attached chiplets. The chiplets may share processing and memory resources of the base die. Routing blockages are minimal, improving signal quality and timing. The system can operate at dual or quad data rates. The architecture facilitates ASIC, ASSP, and FPGA ICs and neural networks, reducing footprint and power requirements.

An integrated circuit emulating a neural system and a fabricating method thereof are provided. A synapse device array that imitates a brain neural system (i.e., a central nervous system) requiring high integration on the same substrate is formed by stacking one or more layers on a lower portion, and a neuron circuit of a peripheral nervous system having sensory and motor neurons connected to the brain neural system is formed on an upper portion.

A method for bonding a first substrate and a second substrate includes: forming a protrusion at a partial region of the first substrate; measuring a position of the first substrate after the protrusion is formed in the first substrate; and bonding the first substrate and the second substrate by contacting the protrusion of the first substrate with a surface of the second substrate to form a contact region and enlarging the contact region.

Gallium nitride (GaN) three-dimensional integrated circuit technology is described. In an example, an integrated circuit structure includes a layer including gallium and nitrogen, a plurality of gate structures over the layer including gallium and nitrogen, a source region on a first side of the plurality of gate structures, a drain region on a second side of the plurality of gate structures, the second side opposite the first side, and a drain field plate above the drain region wherein the drain field plate is coupled to the source region. In another example, a semiconductor package includes a package substrate. A first integrated circuit (IC) die is coupled to the package substrate. The first IC die includes a GaN device layer and a Si-based CMOS layer.

In some embodiments, the present disclosure relates to a device that includes a silicon-on-insulator (SOI) substrate. A first semiconductor device is disposed on a frontside of the SOI substrate. An interconnect structure is arranged over the frontside of the SOI substrate and coupled to the first semiconductor device. A shallow trench isolation (STI) structure is arranged within the frontside of the SOI substrate and surrounds the first semiconductor device. First and second deep trench isolation (DTI) structures extend from the STI structure to an insulator layer of the SOI substrate. Portions of the first and second DTI structures are spaced apart from one another by an active layer of the SOI substrate. A backside through substrate via (BTSV) extends completely through the SOI substrate from a backside to the frontside of the SOI substrate. The BTSV is arranged directly between the first and second DTI structures.

An integrated device, the device including: a first level including a first mono-crystal layer, the first mono-crystal layer including a plurality of single crystal transistors; an overlying oxide disposed on top of the first level; a second level including a second mono-crystal layer, the second level overlaying the oxide, where the second mono-crystal layer includes a plurality of image sensors, where the second level is bonded to the first level including an oxide to oxide bond; a plurality of pixel control circuits; a third level disposed underneath the first level, where the third level includes a plurality of third transistors, where the plurality of third transistors each include a single crystal channel; and a plurality of recessed channel transistors.

Methods, systems, and devices implementing techniques for dicing bonded wafers using laser technologies are described. A bonded wafer includes an optically transmissive substrate bonded with a semiconductor substrate. The optically transmissive substrate is irradiated using a first laser technology associated with perforating the optically transmissive substrate to form damage tracks. The semiconductor substrate is irradiated using a second laser technology associated with forming damage regions within the semiconductor substrate. The damage regions of the semiconductor substrate are aligned with the damage tracks of the optically transmissive substrate during irradiation of the semiconductor substrate or the optically transmissive substrate, forming an aligned region through the bonded wafer with a relatively high likelihood for fracture. After irradiating the optically transmissive substrate and the semiconductor substrate, one or more forces may be applied to the bonded wafer to separate the bonded wafer into respective dies along the aligned region.

A method for manufacturing a semiconductor device includes the steps of a first separation process of separating the semiconductor layer from the first substrate by bringing a pick-up substrate into close contact with the semiconductor layer and then moving the pick-up substrate away from the first substrate, pressing of pressing the semiconductor layer that is in close contact with the pick-up substrate to the second substrate, temperature maintenance of maintaining temperatures of contact surfaces of the semiconductor layer and the second substrate at a temperature higher than room temperature while pressing the semiconductor layer onto the second substrate, and a second separation process of separating the semiconductor layer from the pick-up substrate after the temperatures of the contact surfaces are maintained at the temperature higher than room temperature.