Integrated circuit emulating neural system with neuron circuit and synapse device array and fabrication method thereof

Abstract

An integrated circuit emulating a neural system and a fabricating method thereof are provided. A synapse device array that imitates a brain neural system (i.e., a central nervous system) requiring high integration on the same substrate is formed by stacking one or more layers on a lower portion, and a neuron circuit of a peripheral nervous system having sensory and motor neurons connected to the brain neural system is formed on an upper portion.

Claims

1. An integrated circuit emulating a neural system comprising: a substrate; synapse device layers stacked vertically; insulating film disposed so that the insulating film is on the substrate and between the synapse device layers; and a neuron circuit layer composed of a plurality of neuron circuit blocks, the neuron circuit blocks being disposed over the synapse device layers such that the insulating film is between the neuron circuit blocks and the synapse device layers, wherein each of the synapse device array layers comprises a plurality of synapse mimetic devices, and wherein there are more of the synapse device layers than the neuron circuit layer.

2. The integrated circuit emulating a neural system of claim 1, wherein the synapse device layers and the neuron circuit layer are polysilicon layers.

3. The integrated circuit emulating a neural system of claim 2, wherein each of the polysilicon layers has a thickness of 3 m or less.

4. The integrated circuit emulating a neural system of claim 1, wherein the plurality of synapse mimetic devices are floating body devices that imitate long-term and short-term memories of brain cells, and wherein the neuron circuit layer has sensory and motor neuron mimetic devices electrically connected to one or more of the synapse mimetic devices.

Description

BRIEF DESCRIPTION OF THE DRAWINGS

(1) FIGS. 1(a)-(c) and 3(a)-3(c) show a concept of a conventional semiconductor integrated system techniques, in which the FIG. 1(a) shows a technique of stacking chips, the FIGS. 1(b) and 3(a) show a wafer-to-wafer technique, FIG. 1(c) shows heterogeneous integrated technique for microsystem, FIG. 3(b) shows chip-to-wafer manufacturing technique, and FIG. 3(c) shows a heterogeneous semiconductor substrate boding technique.

(2) FIG. 2 is a table showing advantages and disadvantages of the conventional boding technique.

(3) FIGS. 4 to 8 are schematic process views according to an embodiment of the present invention.

(4) FIG. 9 is a cross-sectional view of an integrated circuit emulating a neural system according to an embodiment of the present invention.

(5) In these drawings, the following reference numbers are used throughout: reference number 10 indicates a substrate, 20, 22, 24, 26 and 28 a synapse device array (layer), 14 a drain supporter, 30 an interlayer insulating film, 42 a neuron circuit block, 50 a connection plug and 60 wiring.

DETAILED DESCRIPTION

(6) Detailed descriptions of preferred embodiments of the present invention are provided below with accompanying drawings.

(7) An integrated circuit emulating a neural system according to the present invention comprises, as commonly shown in FIGS. 7 to 9, a predetermined substrate 10 or 12 and 14; a synapse device array layer 20 formed by stacking one or more layers 22, 24, 26 and 28 interlaying with an interlayer insulating film 30 on the substrate 10; and a neuron circuit layer 42 formed on the synapse device array layer 20 interlaying with an insulating film 30.

(8) Here, the substrate 10 may be made of any insulting material and, as shown in FIG. 9, may be a substrate deposited with an oxide film 14 on a semiconductor substrate 12 such as a silicon substrate, etc.

(9) The synapse device array layer may have a plurality of synapse mimetic devices and can be formed as one layer 20 on the substrate 10, as in the embodiment of FIG. 7. However, as in the embodiment of FIG. 8, it can be formed as two or more layers 22, 24, 26 and 28 interlaying with an interlayer insulating film 30.

(10) The plurality of synapse mimetic devices may be formed of any devices that imitate long-term memory and short-term memory of brain cells. For example, a floating body device developed by one of the present inventors in Korean Patent No. 10-1528802 can be used. By forming a synapse device array layer with a plurality of synapse mimetic devices that imitate the long- and short-term memories of brain cells, it is possible to implement an integrated circuit emulating a neural system capable of deep learning.

(11) The neuron circuit layer may have sensory and motor neuron mimetic devices electrically connected to one or more of the synapse mimetic devices. As shown in FIGS. 7 and 8, the neuron circuit layer can be formed of a plurality of neuron circuit blocks 42 on the synapse device array layer 20; 22, 24, 26 and 28.

(12) The sensory neuron mimetic circuit among the plurality of neuron circuit blocks 42 can comprise a receiver (i.e., a sensory receptor) receiving external stimuli, a sensory neuron mimetic device converting the external stimuli received from the receiver into electric signals, and a signal transporter collecting the electric signals received from the sensory neuron mimetic device and transferring them to one or more of the synapse mimetic devices.

(13) The motor neuron mimetic circuit among the plurality of neuron circuit blocks 42 can comprise a motor neuron mimetic device converting electric signals received from one or more of the synapse mimetic devices into output signals (such as a muscle stimulus, etc.) and an output portion receiving the output signals and displaying them on the outside.

(14) Electrical connection between the neuron circuit layer 42 and the synapse device array layer 20, 22, 24, 26 or 28 can be achieved by etching a part of the upper layer to form a mesa structure. It is preferable that a vertical connection hole (a via hole) penetrating through the interlayer insulating film 30 and/or the lower synapse device array layer 22, 24 or 26 is formed and filled with metal or highly doped polysilicon for the electrical connection.

(15) Especifically, as in the embodiment of FIG. 9, a vertical connection plug 50 for electrical connecting from a sensory and motor neuron mimetic circuit as a neuron circuit block 42 to a plurality of synapse mimetic devices of a synapse device array layer 20 and wirings 60 in the neuron circuit layer and the synapse device array layer can be formed of metal or highly doped polysilicon.

(16) The synapse device array layer 20; 22, 24, 26 and 28 and the neuron circuit layer 42 can be formed of any material capable of implementing a plurality of synapse mimetic devices or sensory and motor neuron mimetic circuits. As shown in FIGS. 6 and 8, it is preferable that polysilicon layers 40 as the synapse device array layer 20; 22, 24, 26 and 28 and the neuron circuit layer 42 are repeatedly stacked on the substrate 10 interlaying with an interlayer insulating film 30.

(17) At this time, it is preferable that the thickness (t) of each polysilicon layer 40 is 3 m or less to ensure transparency, because it is possible to perform optical alignment with the lower circuit in the process. Further, it is more preferable that the thickness (t) of the polysilicon layer 40 is 100 nm or less in order to improve the gate controlling force of the synapse mimetic devices and sensory or motor neuron mimetic devices formed in each layer.

(18) On the other hand, a fabricating method of an integrated circuit emulating a neural system according to the present invention comprises, as shown in FIG. 8, a first step of forming 1.sup.st to Nth synapse device array with 1.sup.st to Nth polysilicon layer 22, 24, 26 or 28 formed on a predetermined substrate 10 interlaying with an interlayer insulating film 30; and a second step of forming a neuron circuit with an N+1 th polysilicon layer 42 formed on the Nth polysilicon layer 22, 24, 26 or 28 interlaying with an insulating film 30.

(19) Here, N is a natural number equal to or greater than 1. FIGS. 4 to 7 show schematic process views when N=1, and FIG. 8 shows an embodiment when N=4.

(20) The substrate 10 may be made of any insulating material as described above and may be a substrate deposited with an oxide film on a semiconductor substrate such as a silicon substrate, etc.

(21) According to the embodiment of FIGS. 4 to 7, first, as shown in FIG. 4, a first polysilicon layer may be formed directly on a silicon substrate 10 deposited with an oxide film to form a synapse device array 20 and followed by forming an interlayer insulating film 30 as shown in FIG. 5, and then a second polysilicon layer 40 may be formed as shown in FIG. 6.

(22) At this time, the second polysilicon layer 40 is preferably formed to have a thickness (t) of 3 m or less like the first polysilicon layer. As described above, the polysilicon layer 40 has such a thickness that the lower circuit can be seen. By doing this, it is possible to perform optical alignment with the lower circuit (for example, a connection hole formed in the interlayer insulating film to make electrical contact with the lower synapse device array, etc.) in the photolithography process. Further, for the same reason described above, it is more preferable that the thicknesses (t) of the first and second polysilicon layers 40 are all 100 nm or less.

(23) Next, as shown in FIG. 7, in the second polysilicon layer 40, neuron circuits such as sensory and motor neuron mimetic circuits may be formed as a plurality of neuron circuit blocks 42.

(24) FIG. 8 shows an embodiment when N=4. Polysilicon layers 22, 24, 26, and 28 can be repeatedly formed to form synapse device arrays and neuron circuits can be formed on the uppermost layer interlaying with an interlayer insulating film 30. By doing this, it is possible to implement an integrated circuit emulating a neural system such as a human neural system.

(25) That is, the lower polysilicon layers can be repeatedly stacked to form a synapse device array with high integration for about 100 trillion synapse mimetic devices corresponding to a human brain neural system (i.e., a central nervous system) and the upper polysilicon layer can be formed to implement neuron circuits emulating sensory and motor neurons corresponding to a human peripheral nervous system. By doing this, it is possible to implement an integrated circuit emulating a neural system such as a human neural system.

(26) As described above, the integrated circuit emulating a neural system according to the present invention can provide a high-density synapse device array layer with a relatively large number of processes on a lower portion and neuron circuits with little influence on the lower devices by having a large circuit unit area and a relatively small number of processes on an upper portion. By this configuration, the present invention can increase the thermal budget in the processes, ensure stable production and reliability through sequential processes, have the interlayer connection process without high-temperature high-pressure and adhesive material required for the conventional interlayer physical bonding and enhance the integration degree of the circuit emulating a neural system through a three-dimensional stacking on a single substrate.

(27) As described above, by forming the synapse device array layer with a plurality of synapse mimetic devices mimicking the long- and short-term memories of human brain cells, it is possible to implement an integrated circuit emulating a neural system capable of deep learning.

(28) The connecting step of electrically connecting one or more synapse mimetic devices to the sensory and motor neuron mimetic circuits can be performed whenever the interlayer insulating film 30 is formed on the Nth polysilicon layer or can be performed only one time as a connection hole (a via hole) forming process after the N+1th polysilicon layer for neuron circuits is formed. The wirings of each layer can be formed and the connection holes can be filled with metal or highly doped polysilicon.

(29) Of course, after forming each of the interlayer insulating films 30 and a planarization process, the polysilicon layers 22, 24, 26, and 28 may be deposited.

(30) This work was supported by the NanoMaterial Technology Development Program through the National Research Foundation of Korea (NRF) funded by the Ministry of Science, ICT and Future Planning (MSIP) under Grant 2016M3A7B4910348.