An SGT circuit includes a first conductor layer which contains a semiconductor atom, which is in contact with an N.sup.+ region and a P.sup.+ region of a Si pillar, or a TiN layer, and whose outer circumference is located outside an outer circumference of a SiO.sub.2 layer in plan view, and a second conductor layer which contains a metal atom, which is connected to an outer periphery of the first conductor layer, and which extends in a horizontal direction.

Embodiments of three-dimensional memory device architectures and fabrication methods therefore are disclosed. In an example, the memory device includes a substrate having a first layer stack on it. The first layer stack includes alternating conductor and insulator layers. A second layer stack is disposed over the first layer stack where the second layer stack also includes alternating conductor and insulator layers. One or more vertical structures extend through the first layers stack. A conductive material is disposed on a top surface of the one or more vertical structures. One or more second vertical structures extend through the second layer stack and through a portion of the conductive material.

A device includes a substrate. A first nanostructure is over the substrate, and includes a semiconductor having a first resistance. A second nanostructure is over the substrate, is offset laterally from the first nanostructure, is at about the same height above the substrate as the first nanostructure, and includes a conductor having a second resistance lower than the first resistance. A first gate structure is over and wrapped around the first nanostructure, and a second gate structure is over and wrapped around the second nanostructure.

A device includes a substrate. A first nanostructure is over the substrate, and includes a semiconductor having a first resistance. A second nanostructure is over the substrate, is offset laterally from the first nanostructure, is at about the same height above the substrate as the first nanostructure, and includes a conductor having a second resistance lower than the first resistance. A first gate structure is over and wrapped around the first nanostructure, and a second gate structure is over and wrapped around the second nanostructure.

Embodiments of three-dimensional memory device architectures and fabrication methods therefore are disclosed. In an example, the memory device includes a substrate having a first layer stack on it. The first layer stack includes alternating conductor and insulator layers. A second layer stack is disposed over the first layer stack where the second layer stack also includes alternating conductor and insulator layers. One or more vertical structures extend through the first layers stack. A conductive material is disposed on a top surface of the one or more vertical structures. One or more second vertical structures extend through the second layer stack and through a portion of the conductive material.

A memory circuit includes: (i) a semiconductor substrate having a planar surface, the semiconductor substrate having formed therein circuitry for memory operations; (ii) a memory array formed above the planar surface, the memory array having one or more electrodes to memory circuits in the memory array, the conductors each extending along a direction substantially parallel to the planar surface; and (iii) one or more transistors each formed above, alongside or below a corresponding one of the electrodes but above the planar surface of the semiconductor substrate, each transistor (a) having first and second drain/source region and a gate region each formed out of a semiconductor material, wherein the first drain/source region, the second drain/source region or the gate region has formed thereon a metal silicide layer; and (b) selectively connecting the corresponding electrode to the circuitry for memory operations.

Methods and systems for double-sided semiconductor device fabrication. Devices having multiple leads on each surface can be fabricated using a high-temperature-resistant handle wafer and a medium-temperature-resistant handle wafer. Dopants can be introduced on both sides shortly before a single long high-temperature diffusion step diffuses all dopants to approximately equal depths on both sides. All high-temperature processing occurs with no handle wafer or with a high-temperature handle wafer attached. Once a medium-temperature handle wafer is attached, no high-temperature processing steps occur. High temperatures can be considered to be those which can result in damage to the device in the presence of aluminum-based metallizations.

Disclosed is a substrate processing method including: a pressurizing operation of raising a process pressure from a first pressure (P.sub.1) to a second pressure (P.sub.2) that is greater than the atmospheric pressure; a depressurizing operation of lowering the process pressure from a sixth pressure (P.sub.6), which is greater than the atmospheric pressure, to a seventh pressure (P.sub.7); and an annealing operation of changing the process pressure into a preset pressure change pattern between the pressurizing operation and the depressurizing operation, under a temperature atmosphere of a second temperature (T.sub.2) higher than the room temperature. A temperature raising operation of raising a temperature atmosphere from a first temperature (T.sub.1) to the second temperature (T.sub.2) is performed from a preset temperature raising start point (t.sub.1) to a preset temperature raising end point (t.sub.2) while the pressurizing operation is performed or after the pressurizing operation is performed.

An SGT circuit includes a first conductor layer which contains a semiconductor atom, which is in contact with an N.sup.+ region and a P.sup.+ region of a Si pillar, or a TiN layer, and whose outer circumference is located outside an outer circumference of a SiO.sub.2 layer in plan view, and a second conductor layer which contains a metal atom, which is connected to an outer periphery of the first conductor layer, and which extends in a horizontal direction.

An epitaxial wafer and a method of fabricating an epitaxial wafer, the method including providing a semiconductor substrate doped with both boron and germanium such that a sum of boron concentration and germanium concentration is at least 8.5E+18 atoms/cm.sup.3 and the germanium concentration is 6 times or less the boron concentration; forming an epitaxial layer on the semiconductor substrate such that the semiconductor substrate and the epitaxial layer constitute the epitaxial wafer; and annealing the epitaxial wafer for 1 hour or longer at a temperature of 1,000° C. or less.