Epitaxial wafer including boron and germanium and method of fabricating the same

Abstract

An epitaxial wafer and a method of fabricating an epitaxial wafer, the method including providing a semiconductor substrate doped with both boron and germanium such that a sum of boron concentration and germanium concentration is at least 8.5E+18 atoms/cm.sup.3 and the germanium concentration is 6 times or less the boron concentration; forming an epitaxial layer on the semiconductor substrate such that the semiconductor substrate and the epitaxial layer constitute the epitaxial wafer; and annealing the epitaxial wafer for 1 hour or longer at a temperature of 1,000° C. or less.

Claims

1. A method of fabricating an epitaxial wafer, the method comprising: providing a semiconductor substrate doped with both boron and germanium such that a sum of boron concentration and germanium concentration is at least 8.5E+18 atoms/cm.sup.3, the boron concentration is less than 2.2E+19 atoms/cm.sup.3, and the germanium concentration is 6 times or less the boron concentration; forming an epitaxial layer on the semiconductor substrate such that the semiconductor substrate and the epitaxial layer constitute the epitaxial wafer; and annealing the epitaxial wafer for 1 hour or longer at a temperature of 1,000° C. or less.

2. The method as claimed in claim 1, wherein providing the semiconductor substrate includes: forming a silicon ingot including the boron and the germanium; and slicing the silicon ingot to form a silicon substrate.

3. The method as claimed in claim 1, wherein providing the semiconductor substrate includes: forming a silicon ingot doped with one of the boron and the germanium, slicing the silicon ingot to form a silicon substrate doped with the one of the boron and the germanium; and doping the silicon substrate with the other of the boron and the germanium.

4. The method as claimed in claim 1, wherein annealing the epitaxial wafer is performed at a temperature of 900° C. to 950° C. under an atmosphere of an inert gas or a mixed gas of an inert gas and hydrogen gas.

5. The method as claimed in claim 4, wherein annealing the epitaxial wafer includes introducing the semiconductor substrate with oxygen to form a gettering site, the semiconductor substrate having an oxygen concentration of 1.0E+18 atoms/cm.sup.3 or higher.

6. The method as claimed in claim 4, wherein: annealing the epitaxial wafer is performed under the atmosphere of the mixed gas of the inert gas and hydrogen gas, and the hydrogen gas is included in the mixed gas in an amount of 10 volume percent or less.

7. The method as claimed in claim 1, wherein: forming the epitaxial layer includes forming a silicon epitaxial layer using an epitaxial growth process in which the semiconductor substrate is used a seed, and the silicon epitaxial layer has a thickness of 5 μm or higher.

8. The method as claimed in claim 1, further comprising doping the epitaxial layer with boron, wherein a boron concentration of the epitaxial layer is less than the boron concentration of the semiconductor substrate or less than the sum of the boron concentration and the germanium concentration.

9. The method as claimed in claim 1, further comprising thinning the semiconductor substrate after annealing the epitaxial wafer.

10. The method as claimed in claim 9, wherein thinning the semiconductor substrate includes etching the semiconductor substrate by a wet etching process that uses an etchant including hydrofluoric acid (HF), nitric acid (HNO.sub.3), acetic acid (CH.sub.3COOH), and phosphoric acid (H.sub.3PO.sub.4).

11. The method as claimed in claim 1, wherein the germanium concentration in the semiconductor substrate is less than 1.4E+20 atoms/cm.sup.3.

12. The method as claimed in claim 1, wherein annealing the epitaxial wafer is performed at a temperature of 900° C. to less than 950° C. under an atmosphere of an inert gas or a mixed gas of an inert gas and hydrogen gas.

13. A method of fabricating an epitaxial wafer, the method comprising: providing a semiconductor substrate in which boron and germanium are doped at a total concentration of 8.5E+18 atoms/cm.sup.3 or greater and a boron concentration is less than 2.2E+19 atoms/cm.sup.3; performing an epitaxial process in which the semiconductor substrate is used as a seed to form an epitaxial layer on the semiconductor substrate such that the epitaxial layer has a thickness of 5 μm or higher; and annealing the semiconductor substrate for 1 hour or longer at a temperature of 900° C. to 950° C.

14. The method as claimed in claim 13, wherein: germanium atoms substitute for ones of silicon atoms of the semiconductor substrate or ones of silicon and boron atoms of the semiconductor substrate.

15. The method as claimed in claim 13, wherein the germanium concentration in the semiconductor substrate is equal to or less than 6 times the boron concentration in the semiconductor substrate.

16. The method as claimed in claim 13, wherein annealing the semiconductor substrate is performed after forming the epitaxial layer on the semiconductor substrate.

17. The method as claimed in claim 13, further comprising performing a wet etching process to thin the semiconductor substrate after annealing the semiconductor substrate, wherein the wet etching process uses an etchant including hydrofluoric acid (HF), nitric acid (HNO.sub.3), acetic acid (CH.sub.3COOH), and phosphoric acid (H.sub.3PO.sub.4).

18. The method as claimed in claim 13, further comprising doping the epitaxial layer with boron, wherein the boron is included in the epitaxial layer at a concentration of 1.0E+15 atoms/cm.sup.3 or less.

19. The method as claimed in claim 13, wherein the germanium concentration in the semiconductor substrate is 3.0E+18 atoms/cm.sup.3 to 1.6E+19 atoms/cm.sup.3.

20. The method as claimed in claim 13, wherein annealing the epitaxial wafer is performed at a temperature of 900° C. to less than 950° C. under an atmosphere of an inert gas or a mixed gas of an inert gas and hydrogen gas.

Description

BRIEF DESCRIPTION OF THE DRAWINGS

(1) Features will be apparent to those of skill in the art by describing in detail exemplary embodiments with reference to the attached drawings in which:

(2) FIG. 1A illustrates a cross-sectional view of a semiconductor substrate doped with both boron and germanium according to some example embodiments.

(3) FIG. 1B illustrates a schematic diagram of a lattice structure of the semiconductor substrate depicted in FIG. 1A.

(4) FIG. 2A illustrates a cross-sectional view of an epitaxial wafer according to some example embodiments.

(5) FIG. 2B illustrates a schematic diagram of a lattice structure of the epitaxial wafer depicted in FIG. 2A.

(6) FIG. 3A illustrates a cross-sectional view of an epitaxial wafer according to a Comparative Example.

(7) FIGS. 3B and 3C illustrate schematic diagrams of a lattice structure of the epitaxial wafer depicted in FIG. 3A.

(8) FIG. 4 illustrates a graph of a relationship between concentrations of boron and germanium according to some example embodiments.

(9) FIG. 5A illustrates a cross-sectional view of an annealing process on an epitaxial wafer according to some example embodiments.

(10) FIG. 5B illustrates a schematic diagram of a lattice structure of the epitaxial wafer depicted in FIG. 5A.

(11) FIG. 6 illustrates a cross-sectional view of a wet etching process on an epitaxial wafer according to some example embodiments.

(12) FIG. 7A illustrates a cross-sectional view of a semiconductor substrate doped with boron according to some example embodiments.

(13) FIG. 7B illustrates a schematic diagram of a lattice structure of the semiconductor substrate depicted in FIG. 7A.

(14) FIG. 8A illustrates a cross-sectional view of a doping process in which germanium is doped in a semiconductor substrate according to some example embodiments.

(15) FIG. 8B illustrates a schematic diagram of a lattice structure of the semiconductor substrate depicted in FIG. 8A.

DETAILED DESCRIPTION

(16) FIG. 1A illustrates a cross-sectional view of a semiconductor substrate doped with both boron and germanium according to some example embodiments. FIG. 1B illustrates a schematic diagram of a lattice structure of the semiconductor substrate depicted in FIG. 1A.

(17) Referring to FIG. 1A, a semiconductor substrate 10 may be provided. The semiconductor substrate 10 may include a silicon (Si) substrate doped with, e.g., p-type impurities. The p-type impurities may include, e.g., boron (B). In an implementation, the semiconductor substrate 10 may have a boron concentration of, e.g., about 8.5E+18 (8.5×10.sup.15) atoms/cm.sup.3. In an implementation, the semiconductor substrate 10 may be relatively heavily doped with boron, and may have resistivity of about 0.01 Ωcm. The semiconductor substrate 10 may have reduced resistance for low power consumption of semiconductor devices. As discussed above, the semiconductor substrate 10 may be heavily doped with boron and may exhibit the properties described above.

(18) In an implementation, as shown in FIG. 1B, boron may be substitutionally doped in the semiconductor substrate 10. For example, silicon atoms of the semiconductor substrate 10 may be replaced with boron atoms. According to Vegard's law, a solid solution has a lattice constant in proportion to a concentration of solute atoms. A change in lattice constant of silicon (e.g., as a result of doping with boron) in accordance with a variation in concentration of boron may be given by Vergard's law as shown in Equation 1 below. For example, a change in lattice constant between the undoped silicon semiconductor substrate 10 and the silicon semiconductor substrate 10 that has been doped with boron may be calculated according to Equation 1.
Δα.sub.Si—B=α.sub.Si×(R.sub.B−R.sub.Si)/R.sub.Si×C.sub.B/C.sub.Si  [Equation 1]

(19) In Equation 1, α.sub.Si indicates a lattice constant of pure silicon in which any element is not added at all. The lattice constant of pure silicon, α.sub.Si, is about 5.43 Å. R.sub.B indicates an atomic radius of boron, and R.sub.Si indicates an atomic radius of silicon. C.sub.B indicates a boron concentration per unit volume, and C.sub.Si indicates a silicon concentration per unit volume. The atomic radius of boron, R.sub.B, is about 0.88 Å, and the atomic radius of silicon, R.sub.Si, is about 1.17 Å. The silicon concentration per unit volume, C.sub.Si, may be about 5.0E+22 atoms/cm.sup.3. When these numerical values are substituted into Equation 1, Equation 2 may be obtained as follows.
Δα.sub.Si—B=−2.69×10.sup.−23×C.sub.B  [Equation 2]

(20) According to Equation 2, the semiconductor substrate 10 doped with boron may have a reduced lattice constant, and the change in lattice constant of (e.g., boron-doped) silicon, Δα.sub.Si—B, may increase with the boron concentration, C.sub.B. For example, the lattice constant of silicon may decrease when the semiconductor substrate 10 is doped with boron whose atomic size is about 0.75 times that of silicon.

(21) The semiconductor substrate 10 may further include other impurities in addition to boron. In an implementation, the other impurities may include, e.g., germanium (Ge). The semiconductor substrate 10 may include both boron and germanium during the ingot growth thereof. In an implementation, the semiconductor substrate 10 may be obtained by growing and slicing a silicon ingot including both boron and germanium.

(22) In an implementation, as shown in FIG. 1B, germanium may be substitutionally doped in the semiconductor substrate 10. For example, silicon atoms may be replaced with germanium atoms. In an implementation, germanium atoms may replace ones of boron atoms in addition to silicon atoms. Like boron, a change in lattice constant of silicon (e.g., as a result of doping with germanium) in accordance with a variation in concentration of germanium may be given by Vergard's law as shown in Equation 3 below. For example, a change in lattice constant between the undoped silicon semiconductor substrate 10 and the silicon semiconductor substrate 10 that has been doped with germanium may be calculated according to Equation 3.
Δα.sub.Si—Ge=α.sub.Si×(R.sub.Ge-R.sub.Si)/R.sub.Si×C.sub.Ge/C.sub.Si  [Equation 3]

(23) In Equation 3, α.sub.Si, R.sub.Si, and C.sub.Si are the same as those discussed with reference to Equation 1. R.sub.Ge indicates an atomic radius of germanium, and C.sub.Ge indicates a germanium concentration per unit volume. The atomic radius of germanium, R.sub.Ge, is about 1.22 Å. When these numerical values are substituted into Equation 3, Equation 4 may be obtained as follows.
Δα.sub.Si—Ge=4.64×10.sup.−24×C.sub.Ge  [Equation 4]

(24) According to Equation 4, the semiconductor substrate 10 doped with germanium may have an increased lattice constant, and the change in lattice constant of (e.g., germanium-doped) silicon, Δα.sub.Si—Ge, may increase with the germanium concentration, C.sub.Ge. For example, the lattice constant of silicon may increase when the semiconductor substrate 10 is doped with germanium whose atomic size is about 1.04 times that of silicon.

(25) When the semiconductor substrate 10 is doped with both boron and germanium, the semiconductor substrate 10 may have a change in lattice constant given by the following Equation 5, or the sum of Equation 2 and Equation 4.
|Δα.sub.Si—B—Ge|=|−2.69×10.sup.−23×C.sub.B+4.64×10.sup.−24×C.sub.Ge|  [Equation 5]

(26) According to Equation 5, when approximately 6 germanium atoms are present per boron atom, the change in lattice constant of the semiconductor substrate 10, |Δα.sub.Si—B-Ge|, may be about zero. For example, boron-induced strain may be completely or partially relieved by germanium having a concentration of about 6 times or less that of boron. As such, when the semiconductor substrate 10 is doped with both boron and germanium, it may be possible to suppress the change in lattice constant of the semiconductor substrate 10.

(27) In an implementation, a relationship between the boron concentration C.sub.B and the germanium concentration C.sub.Ge may be denoted by Equations 6 and 7 below.
C.sub.B: C.sub.Ge≤1:6  [Equation 6]

(28) In Equation 6, the germanium concentration C.sub.Ge may be at most 6 times the boron concentration C.sub.B. In such a case, the change in lattice constant of the semiconductor substrate 10, |Δα.sub.Si—B—Ge| expressed by Equation 5, may be zero or almost zero. If the germanium concentration C.sub.Ge were to be greater than 6 times the boron concentration C.sub.B, a misfit dislocation could be re-generated in the semiconductor substrate 10.

(29) In an implementation, a sum of the boron concentration and the germanium concentration in the doped semiconductor substrate 10 may be 8.5E+18 atoms/cm.sup.3 or greater, as seen in Equation 7.
C.sub.B+C.sub.Ge≥8.5E+18 atoms/cm.sup.3  [Equation 7]

(30) In an implementation, the minimum value 8.5E+18 atoms/cm.sup.3 may be the same as or similar to an initial concentration of boron in the semiconductor substrate 10.

(31) FIG. 2A illustrates a cross-sectional view of an epitaxial wafer according to some example embodiments. FIG. 2B illustrates a schematic diagram showing a lattice structure of the epitaxial wafer depicted in FIG. 2A.

(32) Referring to FIG. 2A, an epitaxial layer 20 may be formed on the semiconductor substrate 10 to fabricate an epitaxial wafer 30. For example, the epitaxial layer 20 may be formed by an epitaxial process in which the semiconductor substrate 10 is used as a seed. The epitaxial layer 20 may include silicon. In an implementation, the epitaxial layer 20 may have a lattice constant of about 5.43 Å.

(33) In an implementation, p-type impurities such as boron (B) may be doped into the epitaxial layer 20. The epitaxial layer 20 may have a boron concentration that is less than that of the semiconductor substrate 10. In an implementation, boron doped in the epitaxial layer 20 may have a concentration of, e.g., about 1.0E+15 atoms/cm.sup.3 or less. The epitaxial layer 20 may be relatively lightly doped with boron, and may have a resistivity equal to or greater than about 10 Ωcm, which may be higher than resistivity (e.g., about 0.01 Ωcm) of the semiconductor substrate 10 that is relatively heavily doped with boron.

(34) FIG. 3A illustrates a cross-sectional view showing an epitaxial wafer according to a Comparative Example. FIGS. 3B and 3C illustrates schematic diagrams showing a lattice structure of the epitaxial wafer depicted in FIG. 3A.

(35) As shown in FIG. 3A, an epitaxial layer 20p may be formed on a semiconductor substrate 10p doped with boron and not doped with germanium. For example, as shown in FIG. 3B, an epitaxial wafer 30p may be fabricated to have a metastable state in which lattice mismatch possibly occurs between the semiconductor substrate 10p and the epitaxial layer 20p. The epitaxial layer 20p may be subject to tensile strain caused by the lattice mismatch. When the epitaxial layer 20p has a relatively smaller thickness, the epitaxial layer 20p may endure the tensile strain. When the epitaxial layer 20p has a relatively larger thickness, as shown in FIG. 3C, the epitaxial layer 20p may be introduced thereinto with misfit dislocations such as edge dislocations 11p for strain relaxation.

(36) According to some example embodiments, as shown in FIG. 2B, co-doping of boron and germanium may help suppress the change in lattice constant of the semiconductor substrate 10, and thus no lattice mismatch may occur between the semiconductor substrate 10 and the epitaxial layer 20. Accordingly, it may be likely that no misfit dislocations are present in the epitaxial wafer 30.

(37) Referring back to FIGS. 2A and 2B, the change in lattice constant of the semiconductor substrate 10, |Δα.sub.Si—B—Ge| expressed by Equation 5, may be zero or almost zero. Therefore, Equation 5 may be converted into Equation 8 below.
|Δα.sub.Si—B—Ge|=|−2.69×10.sup.−23×C.sub.B+4.64×10.sup.−24×C.sub.Ge|≤δ  [Equation 8]

(38) In Equation 8, δ may indicate a certain constant that denotes the degree of lattice mismatch in the semiconductor substrate 10 on which the epitaxial layer 20 can be formed without the occurrence of misfit dislocations. As discussed below with reference to FIG. 4, 6 may influence a thickness of the epitaxial layer 20.

(39) FIG. 4 illustrates a graph showing a relationship between concentrations of boron and germanium according to some example embodiments. In FIG. 4, a horizontal axis indicates the boron concentration C.sub.B, and a vertical axis indicates the germanium concentration C.sub.Ge.

(40) Referring to FIG. 4, a line L1 may denote a linear function of Equation 6, and doping concentrations of boron and germanium may be selected from a right-side region of the line L1. A line L2 may denote a linear function of Equation 7, and a total doping concentration of boron and germanium may be selected from an upper-side region of the line L2. A line L3 may denote a linear function of Equation 8, and doping concentrations of boron and germanium may be selected from a left-side region of the line L3. For example, the boron concentration C.sub.B and the germanium concentration C.sub.Ge may be selected from a region “A” surrounded by the lines L1, L2, and L3.

(41) The line L3 may translate or move to the left or right depending on a value of 6. When the value of δ decreases, the line L3 may move to the left (S1), and when the value of δ increases, the line L3 may move to the right (S2). In the graph of FIG. 4, the phrase “the value of δ decreases” means “the germanium concentration C.sub.Ge becomes proportionally larger” and vice versa. This situation may suggest that germanium alleviates strain caused by boron, and that an increase in germanium concentration C.sub.Ge accelerates relaxation of strain.

(42) An increase in germanium concentration C.sub.Ge may accelerate relaxation of strain, and a high concentration of germanium may facilitate the formation of the epitaxial layer 20 with a large thickness. For example, the epitaxial layer 20 may be formed to have a thickness of 5 μm to 20 μm without the occurrence of misfit dislocations. In an implementation, the epitaxial layer 20 may also be formed to have a thickness greater than about 20 μm without the occurrence of misfit dislocations.

(43) FIG. 5A illustrates a cross-sectional view showing an annealing process on an epitaxial wafer according to some example embodiments. FIG. 5B illustrates a schematic diagram showing a lattice structure of the epitaxial wafer depicted in FIG. 5A.

(44) Referring to FIG. 5A, after the epitaxial layer 20 is formed, a post-epitaxy annealing process may be performed. The post-epitaxy annealing process may be carried out to increase gettering efficiency of the semiconductor substrate 10 and/or quality of the epitaxial layer 20.

(45) To obtain gettering efficiency, an oxygen precipitate (OP) or a bulk micro defect (BMD) may be formed. The formation of the oxygen precipitate and the bulk micro defect may need oxygen and vacancies within the semiconductor substrate 10 as shown in Equations 9 and 10 below.
OP nucleation: Si(s)+2Oi+Vacancy.fwdarw.SiO.sub.2  [Equation 9]

(46) In Equation 9, Oi may indicate interstitial oxygen introduced into an interstitial site between lattices.
OP growth: nSiO.sub.2.fwdarw.BMD(n≥50)  [Equation 10]

(47) The interstitial oxygen Oi may be introduced during or after the formation of the semiconductor substrate 10 and may have a concentration equal to or greater than about 1.0E+18 atoms/cm.sup.3. When the semiconductor substrate 10 is doped with both boron and germanium, a large number of vacancies may be formed in the semiconductor substrate 10. For example, as shown in FIG. 5B, the semiconductor substrate 10 may be advantageous to the formation of the oxygen precipitate.

(48) In an implementation, the oxygen precipitate may be nucleated in the epitaxial growth process for the formation of the epitaxial layer 20 shown in FIG. 2A, and then may be grown in the post-epitaxy annealing process shown in FIG. 5A. A compressive strain may be generated around the oxygen precipitate or the bulk micro defect, and as a result, the oxygen precipitate or the bulk micro defect may serve as a gettering site to gather metal contamination. For example, the epitaxial wafer 30 may increase in intrinsic gettering efficiency.

(49) The post-epitaxy annealing process may help reduce roughness of a surface 20s of the epitaxial layer 20 and also may help remove defects from the epitaxial layer 20. When the post-epitaxy annealing process is performed at high temperatures, the bulk micro defect may exponentially increase in size and the epitaxial layer 20 may increase in surface smoothing effect.

(50) Boron may be trapped by germanium as a co-dopant, and then turn into a boron-germanium pair, which may result in a reduction in diffusivity of boron. For example, the higher concentration of germanium, the lower diffusivity of boron. However, when the post-epitaxy annealing process is performed at high temperatures, the diffusivity of boron may become larger. For example, the post-epitaxy annealing process may be performed at temperatures sufficient to suppress side effects (e.g., out-diffusion of boron) caused by the diffusion of boron.

(51) In an implementation, the post-epitaxy annealing process may be performed for about 1 hour or longer at a temperature equal to or less than about 1,000° C., e.g., about 900° C. to about 950° C. Preferably, the post-epitaxy annealing process may be performed for 1 hour. Even when the post-epitaxy annealing process is performed only once, it may be possible to reduce diffusion of boron while improving gettering efficiency and surface smoothing effect. The post-epitaxy annealing process may be performed under an atmosphere of an inert gas (e.g., Ar), or a mixed gas of hydrogen (H.sub.2) and an inert gas (e.g., Ar). Hydrogen (H.sub.2) may be included in the mixed gas in an amount of about 10 volume percent or less.

(52) The epitaxial wafer 30 shown in FIG. 5A may be utilized to fabricate an image sensor. To measure distances or recognize human faces, an infrared (IR) sensor may use light with a long wavelength (e.g., about 940 nm) beyond a wavelength band (e.g., about 810 nm) perceptible to human eyes. However, an increase in wavelength of light may decrease absorption efficiency of silicon and in turn may reduce quantum efficiency. For example, a relatively thick photodiode may be formed, or a thick epitaxial layer free of defects may be formed.

(53) In an implementation, as discussed above with reference to FIG. 4, the epitaxial layer 20 may be formed to have a thickness of about 5 μm to about 20 μm, or equal to or greater than about 20 μm, without the occurrence of misfit dislocations. For example, the epitaxial wafer 30 of an embodiment may be employed to fabricate an image sensor that uses light with a long wavelength (e.g., about 940 nm).

(54) A wet etching process may be performed to reduce a thickness of the epitaxial wafer 30 so as to manufacture a backside illumination (BSI) image sensor with improved photosensitivity. This will be discussed below with reference to FIG. 6.

(55) FIG. 6 illustrates a cross-sectional view showing a wet etching process on an epitaxial wafer according to some example embodiments.

(56) Referring to FIG. 6, the semiconductor substrate 10 may be thinned by a wet etching process that uses an etchant including, e.g., hydrofluoric acid (HF), nitric acid (HNO.sub.3), acetic acid (CH.sub.3COOH), and phosphoric acid (H.sub.3PO.sub.4). As shown in Equation 11 below, nitric acid (HNO.sub.3) may be used as an oxidizing agent that oxidizes silicon (Si) into silicon oxide (SiO.sub.2); silicon oxide (SiO.sub.2) may react with hydrofluoric acid (HF) and then be etched.
18HF+4HNO.sub.3+3Si.fwdarw.3H.sub.2SiF.sub.6(aq)+4NO+8H.sub.2O  [Equation 11]

(57) The oxidation reaction caused by nitric acid (HNO.sub.3) may be the slowest reaction that determines the overall reaction rate. Acetic acid (CH.sub.3COOH) and phosphoric acid (H.sub.3PO.sub.4) may adjust a total amount of nitric acid (HNO.sub.3) and the etchant, thereby controlling the reaction rate.

(58) A silicon substrate heavily doped with boron may be removed at relatively high etch rates. It may be understood that an oxidation reaction that controls etching of the silicon substrate heavily doped with boron may be performed at high rates. Oxidation of silicon-germanium (SiGe) may be faster than oxidation of silicon (Si), and an increase in germanium concentration may raise an etching rate of silicon-germanium (SiGe). A bonding energy between a silicon atom and a germanium atom (Si—Ge) and between germanium atoms (Ge—Ge) may be less than a bonding energy between silicon atoms (Si—Si) and between a silicon atom and a boron atom (Si—B). Based on this fact, it may be found that the semiconductor substrate 10 doped with both boron and germanium may be rapidly etched by the etchant including hydrofluoric acid (HF), nitric acid (HNO.sub.3), acetic acid (CH.sub.3COOH), and phosphoric acid (H.sub.3PO.sub.4). In addition, an etch selectivity may be secured between the semiconductor substrate 10 and the epitaxial layer 20.

(59) As discussed above, the epitaxial wafer 30, including the epitaxial layer 20 formed on the semiconductor substrate 10 doped with both boron and germanium, may be fabricated without the occurrence of misfit dislocations caused by lattice mismatch and without thickness limitation of the epitaxial layer 20, thereby exhibiting superior electrical characteristics. Further, after the formation of the epitaxial layer 20, the post-epitaxy annealing process may be performed to help prevent metal contamination and also to increase quality of the epitaxial layer 20. Moreover, the semiconductor substrate 10 may be wet-etched at high rates, and thus productivity may be increased.

(60) FIG. 7A illustrates a cross-sectional view showing a semiconductor substrate doped with boron according to some example embodiments. FIG. 7B illustrates a schematic diagram showing a lattice structure of the semiconductor substrate depicted in FIG. 7A.

(61) Referring to FIG. 7A, a semiconductor substrate 10 doped with boron (B) may be provided. As shown in FIG. 7B, boron may be substitutionally doped in the semiconductor substrate 10. Boron may be heavily doped at a concentration of about 8.5E+18 atoms/cm.sup.3, and the semiconductor substrate 10 may have resistivity of about 0.01 Ωcm. The previous descriptions associated with Equations 1 and 2 may be identically or similarly applicable to the present embodiment.

(62) FIG. 8A illustrates a cross-sectional view showing a germanium doping process on a semiconductor substrate according to some example embodiments. FIG. 8B illustrates a schematic diagram showing a lattice structure of the semiconductor substrate depicted in FIG. 8A.

(63) Referring to FIG. 8A, germanium may be doped in the (boron-doped) semiconductor substrate 10. Thus, it may be possible to obtain the semiconductor substrate 10 doped with both boron and germanium. As shown in FIG. 8B, germanium may be substitutionally doped in the semiconductor substrate 10. The previous descriptions associated with Equations 3 to 7 and FIG. 4 may be identically or similarly applicable to the present embodiment.

(64) In an implementation, as shown in FIGS. 7A and 8A, germanium may be doped in the semiconductor substrate 10 (that has already been doped with boron). In an implementation, boron may be doped in the semiconductor substrate 10 that has already been doped with germanium. In an implementation, one of boron and germanium may be first doped in the semiconductor substrate 10 in which no impurities are doped, and then the other of boron and germanium may be later doped in the semiconductor substrate 10. In an implementation, both boron and germanium may be simultaneously doped in the semiconductor substrate 10 in which no impurities are doped.

(65) As shown in FIGS. 2A and 2B, an epitaxial layer 20 may be formed on the semiconductor substrate 10 to fabricate an epitaxial wafer 30, and as shown in FIGS. 5A and 5B, the epitaxial wafer 30 may undergo a post-epitaxy annealing process. The previous descriptions associated with Equations 8 to 10 may be identically or similarly applicable to the present embodiment.

(66) Like the previous embodiments, the epitaxial wafer 30 may be used to fabricate an image sensor. Furthermore, a wet etching process may be performed on the epitaxial wafer 30 to fabricate a backside illumination (BSI) image sensor.

(67) By way of summation and review, to utilize long-wavelength light, thicknesses of photodiodes may increase. An increase in thicknesses of epitaxial layers may be used to increase thicknesses of photodiodes. Misfit dislocations could be generated due to lattice mismatch between an epitaxial layer and a semiconductor substrate.

(68) According to an embodiment, a semiconductor substrate doped with both boron and germanium may be fabricated to help reduce or eliminate lattice mismatch between the semiconductor substrate and its overlying epitaxial layer. Accordingly, it may be possible to prevent the occurrence of misfit dislocations caused by lattice mismatch and thus to obtain an epitaxial wafer with excellent electrical characteristics.

(69) In addition, an annealing process may be performed after the formation of the epitaxial layer, and as a result, the epitaxial wafer may be fabricated while preventing metal contamination and also to have superior gettering efficiency. In addition, the epitaxial layer may be formed to have a thickness as large as desired, and thus it may be possible to manufacture an image sensor using long-wavelength light.

(70) One or more embodiments may provide an epitaxial wafer free of misfit dislocations due to elimination of lattice mismatch.

(71) One or more embodiments may provide an epitaxial wafer with improved gettering efficiency and effective to prevent metal contamination.

(72) One or more embodiments may provide a method of fabricating an epitaxial wafer, in which method both boron and germanium are doped in a semiconductor substrate.

(73) One or more embodiments may provide a method of fabricating an epitaxial wafer, which method employs a post-epitaxy annealing process.

(74) Example embodiments have been disclosed herein, and although specific terms are employed, they are used and are to be interpreted in a generic and descriptive sense only and not for purpose of limitation. In some instances, as would be apparent to one of ordinary skill in the art as of the filing of the present application, features, characteristics, and/or elements described in connection with a particular embodiment may be used singly or in combination with features, characteristics, and/or elements described in connection with other embodiments unless otherwise specifically indicated. Accordingly, it will be understood by those of skill in the art that various changes in form and details may be made without departing from the spirit and scope of the present invention as set forth in the following claims.