In a manufacturing step in which a structure of target of screening is formed on a semiconductor substrate in the middle of manufacturing process before a semiconductor device is finished, screening of potential defects of a gate insulating film is performed for each wafer at one time so that the semiconductor device is caused to appear as an initial defective product when the finished semiconductor device is subjected to an electrical characteristic test. Provided are a semiconductor device, and a method of manufacturing a semiconductor device which enables reliable screening of potential defects in a short period of time.

A semiconductor device includes a semiconductor part; first and second electrodes respectively on back and front surfaces of the semiconductor part; and a control electrode between the semiconductor part and the second electrode. The control electrode is provided inside a trench of the semiconductor part. The control electrode is electrically insulated from the semiconductor part by a first insulating film and electrically insulated from the second electrode by a second insulating film. The control electrode includes an insulator at a position apart from the first insulating film and the second insulating film. The semiconductor part includes a first layer of a first conductivity type provided between the first and second electrodes, the second layer of a second conductivity type provided between the first layer and the second electrode and the third layer of the first conductivity type selectively provided between the second layer and the second electrode.

An electrical contact structure (an MIS contact) includes one or more conductors (M-Layer), a semiconductor (S-Layer), and an interfacial dielectric layer (I-Layer) of less than 4 nm thickness disposed between and in contact with both the M-Layer and the S-Layer. The I-Layer is an oxide of a metal or a semiconductor. The conductor of the M-Layer that is adjacent to and in direct contact with the I-Layer is a metal oxide that is electrically conductive, chemically stable and unreactive at its interface with the I-Layer at temperatures up to 450° C. The electrical contact structure has a specific contact resistivity of less than or equal to approximately 10.sup.−5-10.sup.−7 Ω-cm.sup.2 when the doping in the semiconductor adjacent the MIS contact is greater than approximately 2×10.sup.19 cm.sup.−3 and less than approximately 10.sup.−8 Ω-cm.sup.2 when the doping in the semiconductor adjacent the MIS contact is greater than approximately 10.sup.20 cm.sup.−3.

A method for preserving interlevel dielectric in a gate cut region includes recessing a dielectric fill to expose cap layers of gate structures formed in a device region and in a cut region and forming a liner in the recess on top of the recessed dielectric fill. The liner includes a material to provide etch selectivity to protect the dielectric fill. The gate structures in the cut region are recessed to form a gate recess using the liner to protect the dielectric fill from etching. A gate material is removed from within the gate structure using the liner to protect the dielectric fill from etching. A dielectric gap fill is formed to replace the gate material and to fill the gate recess in the cut region.

A ferroelectric memory device includes an alternating stack of insulator layers and electrically conductive layers and located over a top surface of a substrate, a memory stack structure vertically extending through the alternating stack and including a ferroelectric material layer, a front-side gate dielectric contacting the ferroelectric material layer, and a vertical semiconductor channel contacting the front-side gate dielectric, a backside gate dielectric contacting the vertical semiconductor channel, and a backside gate electrode contacting the backside gate dielectric. Portions of the ferroelectric material layer adjacent to the electrically material layers can be programmed with polarization states to store data.

An insulated gate turn-off (IGTO) device, formed as a die, has a layered structure including a p+ layer (e.g., a substrate), an n epi layer, a p-well, trenched insulated gate regions formed in the p-well, and n+ regions between the gate regions, so that vertical NPN and PNP transistors are formed. The device may be formed of a matrix of cells or may be interdigitated. To turn the device on, a positive voltage is applied to the gate, referenced to the cathode. The cells further contain a vertical p-channel MOSFET, for rapidly turning the device off. The p-channel MOSFET may be made a depletion mode device by implanting boron ions at an angle into the trenches to create a p-channel. This allows the IGTO device to be turned off with a zero gate voltage while in a latch-up condition, when the device is acting like a thyristor.

The disclosure provides dyes for marking hydrocarbon compositions. More particularly, the disclosure relates to non-mutagenic dyes for marking hydrocarbon compositions.

An insulated gate turn-off (IGTO) device, formed as a die, has a layered structure including a p+ layer (e.g., a substrate), an n epi layer, a p-well, trenched insulated gate regions formed in the p-well, and n+ regions between the gate regions, so that vertical NPN and PNP transistors are formed. The device may be formed of a matrix of cells or may be interdigitated. To turn the device on, a positive voltage is applied to the gate, referenced to the cathode. The cells further contain a vertical p-channel MOSFET, for rapidly turning the device off. The p-channel MOSFET may be made a depletion mode device by implanting boron ions at an angle into the trenches to create a p-channel. This allows the IGTO device to be turned off with a zero gate voltage while in a latch-up condition, when the device is acting like a thyristor.

The present subject matter discloses a longitudinal silicon ingot slicing apparatus for lateral slicing of cylindrical ingot to maximize resulting chips yield as compared to the conventional transverse slicing of ingot. The resulting rectangular wafers made from lateral slicing of ingot maximizes yield as by the lateral slicing of ingot, overall chips per wafer ratio gets increased as compared to transversal cutting while the said apparatus and method decreases waste due to conflict between chip and wafer geometry. The novel apparatus of longitudinal slicing of cylindrical ingot is comprising of a wire wounded around a wire reels and a plurality of grooved rollers to form a wire raw to slice the cylindrical silicon ingot. A motors are connected with the wire reels and with at least one grooved roller to slide the wire row back and forth to cut the cylindrical ingot. A work feed table is also configured along with the JIG fixture that holds the cylindrical ingot as well as align the wire raw during slicing.

The disclosure provides dyes for marking hydrocarbon compositions. More particularly, the disclosure relates to non-mutagenic dyes for marking hydrocarbon compositions.