Abstract
An insulated gate turn-off (IGTO) device, formed as a die, has a layered structure including a p+ layer (e.g., a substrate), an n epi layer, a p-well, trenched insulated gate regions formed in the p-well, and n+ regions between the gate regions, so that vertical NPN and PNP transistors are formed. The device may be formed of a matrix of cells or may be interdigitated. To turn the device on, a positive voltage is applied to the gate, referenced to the cathode. The cells further contain a vertical p-channel MOSFET, for rapidly turning the device off. The p-channel MOSFET may be made a depletion mode device by implanting boron ions at an angle into the trenches to create a p-channel. This allows the IGTO device to be turned off with a zero gate voltage while in a latch-up condition, when the device is acting like a thyristor.
Claims
1-20. (canceled)
21. An electronic device formed as a die comprising: a semiconductor material; an array of cells in the semiconductor material comprising: one or more trenches in the semiconductor material, the one or more trenches having sidewalls; a first p-type region abutting at least a bottom of the one or more trenches; a plurality of elongated first n-type regions overlying the first p-type region, the first n-type regions abutting the trench sidewalls, wherein each of the first n-type regions is substantially surrounded by a trench, the first n-type regions having a first top surface; a first dielectric layer having an elongated contact opening that exposes portions of the first top surface of the first n-type regions, the contact opening having long sides and short sides, the long sides of the contact opening being substantially perpendicular to the elongated first n-type regions and extending over multiple ones of the first n-type regions; a cathode electrode electrically contacting the first top surface of the first n-type regions through the contact opening; a dielectric layer along the sidewalls of the one or more trenches; and a conductive material at least partially filling the one or more trenches to form one or more gates for one or more turn-on MOSFETs, wherein a sufficiently positive voltage applied to the one or more gates turns on the electrical device to conduct a current between a top of the electrical device and a bottom of the electrical device, the long sides of the contact opening being substantially perpendicular to the one or more gates.
22. The device of claim 21 wherein the first p-type region is a base of a vertical npn bipolar transistor, and wherein the one or more turn-on MOSFETs reduce a base width of the npn bipolar transistor to turn on the device when the sufficiently positive voltage is applied to the one or more gates.
23. The device of claim 21 further comprising: a plurality of second p-type regions overlying portions of the first n-type regions and abutting upper portions of the trench sidewalls, the second p-type regions having a second top surface between the first top surface of the first n-type regions; wherein the first dielectric layer elongated contact opening also exposes portions of the second top surface of the second p-type regions, wherein the cathode electrode also contacts the second top surface of the plurality of second p-type regions, and wherein the first p-type region, the second p-type regions, and the one or more gates form one or more turn-off MOSFETs, such that the one or more turn-on MOSFETs and the one or more turn-off MOSFETs use the same one or more gates, wherein a voltage applied to the one or more gates sufficiently below the positive voltage causes the one or more turn-off MOSFETs to conduct a current between the plurality of second p-type regions and the first p-type region to turn off the electrical device.
24. The device of claim 23 wherein the device comprises at least a vertical bipolar transistor having an emitter and a base, wherein the voltage applied to the one or more gates sufficiently below the positive voltage causes the one or more turn-off MOSFETs to electrically connect the emitter to the base to turn off the bipolar transistor, which turns off the device.
25. The device of claim 24 wherein the one or more turn-off MOSFETs are depletion mode turn-off MOSFETs when conducting the current between the plurality of second p-type regions and the first p-type region to turn off the electrical device.
26. The device of claim 24 wherein the one or more turn-off MOSFETs are enhancement mode turn-off MOSFETs when conducting the current between the plurality of second p-type regions and the first p-type region to turn off the electrical device.
27. The device of claim 21 wherein the device comprises an Insulated Gate Turn Off (IGTO) device.
28. The device of claim 21 wherein the device comprises an Insulated Gate Bipolar Transistor (IGBT).
29. The device of claim 21 wherein the device comprises vertical npnp layers forming a vertical npn transistor and a vertical pnp transistor, wherein vertical conduction of the device occurs when a product of the betas of the npn transistor and the pnp transistor exceeds one.
30. The device of claim 21 wherein the one or more trenches substantially surround the first top surface of the first n-type regions.
31. An electronic device formed as a die comprising: a semiconductor material; an array of cells in the semiconductor material comprising: one or more trenches in the semiconductor material, the one or more trenches having sidewalls; a first p-type region abutting at least a bottom of the one or more trenches; a first n-type region overlying the first p-type region, the first n-type region abutting the trench sidewalls, wherein the one or more trenches substantially surround the first n-type region, the first n-type region and the one or more trenches forming interdigitated fingers, the first n-type region having a first top surface; a first dielectric layer having an elongated contact opening that exposes portions of the first top surface of the first n-type region; a cathode electrode electrically contacting the first top surface of the first n-type region through the contact opening; a dielectric layer along the sidewalls of the one or more trenches; and a conductive material at least partially filling the one or more trenches to form one or more gates for one or more turn-on MOSFETs, wherein a sufficiently positive voltage applied to the one or more gates turns on the electrical device to conduct a current between a top of the electrical device and a bottom of the electrical device.
32. The device of claim 31 wherein the first p-type region is a base of a vertical npn bipolar transistor, and wherein the one or more turn-on MOSFETs reduce a base width of the npn bipolar transistor to turn on the device when the sufficiently positive voltage is applied to the gates.
33. The device of claim 31 further comprising: a plurality of second p-type regions having a second top surface that is surrounded by the first top surface of the first n-type regions; wherein the first dielectric layer elongated contact opening also exposes portions of the second top surface of the second p-type regions, wherein the cathode electrode also contacts the second top surface of the plurality of second p-type regions, and wherein the first p-type region, the second p-type regions, and the one or more gates form one or more turn-off MOSFETs, such that the one or more turn-on MOSFETs and the one or more turn-off MOSFETs use the same one or more gates, wherein a voltage applied to the one or more gates sufficiently below the positive voltage causes the one or more turn-off MOSFETs to conduct a current between the plurality of second p-type regions and the first p-type region to turn off the electrical device.
34. The device of claim 33 wherein the device comprises at least a vertical bipolar transistor having an emitter and a base, wherein the voltage applied to the one or more gates sufficiently below the positive voltage causes the one or more turn-off MOSFETs to electrically connect the emitter to the base to turn off the bipolar transistor, which turns off the device.
35. The device of claim 34 wherein the one or more turn-off MOSFETs are depletion mode turn-off MOSFETs when conducting the current between the plurality of second p-type regions and the first p-type region to turn off the electrical device.
36. The device of claim 34 wherein the one or more turn-off MOSFETs are enhancement mode turn-off MOSFETs when conducting the current between the plurality of second p-type regions and the first p-type region to turn off the electrical device.
37. The device of claim 31 wherein the device comprises an Insulated Gate Turn Off (IGTO) device.
38. The device of claim 31 wherein the device comprises an Insulated Gate Bipolar Transistor (IGBT).
39. The device of claim 31 wherein the device comprises vertical npnp layers forming a vertical npn transistor and a vertical pnp transistor, wherein vertical conduction of the device occurs when a product of the betas of the npn transistor and the pnp transistor exceeds one.
Description
BRIEF DESCRIPTION OF THE DRAWINGS
[0025] FIG. 1 is a cross-section of a small portion of an IGTO device of a type described in the assignee's U.S. Pat. No. 9,391,184.
[0026] FIG. 2 is a top down view of the area between the two gates in FIG. 1.
[0027] FIG. 3 is taken across the IGTO device along line 3-3 in FIG. 2.
[0028] FIG. 4 is taken across the IGTO device along line 4-4 in FIG. 2.
[0029] FIG. 5 illustrates a normalized forward voltage (Vf) curve and a normalized turn-off time curve versus the percentage area of the pull-down MOSFET area.
[0030] FIG. 6 is identical to FIG. 1 but identifies the gate-to-gate spacing and the required minimum contact opening in any top dielectric layer for the cathode metal to contact both the p+ regions and the n+ source.
[0031] FIG. 7 illustrates the effect of gate-to-gate spacing on Vf for three cathode-anode voltages.
[0032] FIG. 8 is a top down view of a portion of a cell of an IGTO device between two vertical gates.
[0033] FIG. 9 is taken across line 9-9 in FIG. 8.
[0034] FIG. 10 is taken across line 10-10 in FIG. 8.
[0035] FIG. 11 illustrates another design of the p+ region relative to the n+ source.
[0036] FIG. 12 is taken across line 12-12 in FIG. 11.
[0037] FIG. 13 is taken across line 13-13 in FIG. 11.
[0038] FIG. 14 illustrates an embodiment of an IGTO device, where the n layer in FIGS. 1, 9, and 12 is not formed below the n+ source.
[0039] FIG. 15 is taken across line 15-15 in FIG. 14.
[0040] FIG. 16 is taken across line 16-16 in FIG. 14.
[0041] FIG. 17 is a top down view of a portion of two cells between opposing gates in an IGTO device.
[0042] FIG. 18 is a cross-section along line 18-18 in FIG. 17.
[0043] FIG. 19 is a cross-section along line 19-19 in FIG. 17.
[0044] FIG. 20 is a cross-section along line 20-20 in FIG. 17.
[0045] FIGS. 21-24 are process flow cross-sections across a single cell in an IGTO device to illustrate a technique to form a self-aligned cathode metal without having to form a contact opening.
[0046] FIG. 25 is similar to FIG. 1 except that a depletion mode pull-down MOSFET is formed, rather than an enhancement mode pull-down MOSFET.
[0047] FIG. 26 is a cross-section of an empty trench formed in an n-type epi layer, such as the n-type epi layer of FIG. 21.
[0048] FIG. 27 illustrates the formation of the resulting narrow p region that will be the channel of the depletion mode pull-down MOSFET.
[0049] FIG. 28 illustrates various features being formed, as described with respect to FIGS. 21-24.
[0050] FIG. 29 illustrates one possible top down view of the active area in FIG. 28.
[0051] FIG. 30 illustrates another embodiment of a top down view of the active area in FIG. 28 showing the p+ region and n+ source.
[0052] FIG. 31 illustrates the angled implantation of boron into both sidewalls of the trench to form a depletion mode pull-down MOSFET on both sides of a cell for improved turn-off time.
[0053] FIG. 32 illustrates one possible top down view of the active area of an IGTO device having the depletion mode pull-down MOSFET on both sides of a cell, formed using the dual angled implants of FIG. 31.
[0054] FIG. 33 is a top down view of the active area of an IGTO device cell, showing the n+ sources and the p+ region formed as a horizontal strip.
[0055] FIG. 34 is taken along line 34-34 in FIG. 33.
[0056] FIG. 35 is taken along line 35-35 in FIG. 33.
[0057] FIG. 36 is a top down view of the active area of an IGTO device cell, showing the n+ sources and the p+ region formed as a horizontal strip.
[0058] FIG. 37 is taken along line 37-37 in FIG. 36.
[0059] FIG. 38 is taken along line 38-38 in FIG. 36.
[0060] FIG. 39 is a top down view of an array of four cells.
[0061] FIG. 40 is a top down view of a cell of an IGTO device, where the gate and the n+ source have interdigitated fingers for abutting along a very large surface area for high efficiency and low Vf.
[0062] Elements that are the same or equivalent are labelled with the same numerals.
DETAILED DESCRIPTION
[0063] The novel cell designs and MOSFET structures described below can also be used in vertical devices other than the type of IGTO device shown in FIG. 1. For example, the designs and structures could also improve the performance of insulated gate bipolar transistor (IGBT) devices.
[0064] FIG. 8 is a top down view of a portion of a cell of an IGTO device between two vertical gates. FIG. 9 is taken across line 9-9 in FIG. 8, and FIG. 10 is taken across line 10-10 in FIG. 8.
[0065] FIGS. 9 and 10 do not show any part of the cell below the p-well 14, but the remainder may be similar to that shown in FIG. 1, where the n-type layers 26 and 28 and p+ substrate 34 are below the p-well 14. In another embodiment, the gate may extend completely through the p-well 14 (rather than terminate within the p-well 14), causing the device to be similar to an IGBT. This gate extension to form an IGBT applies to all the embodiments.
[0066] One significant difference between the configurations of the p+ region 52 and the n+ sources 54 and 55 of FIG. 8 and the p+ region 36 and the n+ source 32 of FIG. 2 is that there is a gap between the two n+ sources 54 and 55. Within the gap is a portion of the p+ region 52. The p+ region 52 forms part of the pull-down MOSFET used for rapidly turning off the IGTO device. The area of the p+ region 52 surrounding the n+ sources 54 and 55 and abutting the gates may be made much narrower to reduce pinching off the electron flow and allow closer gate-to-gate spacing. Hence, the most relevant aspect of FIG. 8 is the horizontal layout of the p+ region 52 between the n+ sources 54 and 55, which extends to the sides of the gates. The remainder of the p+ region 52 can even be deleted to increase the percentage area of the n+ sources 54 and 55 along the gates to improve the forward voltage Vf.
[0067] The contact opening 58 in the dielectric 60 (FIG. 9) can be very narrow since the cathode metal (over the dielectric 60 and in the contact opening 58) only needs to directly contact a portion of the horizontal strip of the p+ region 52 and the n+ sources 54 and 55. This enables the gate-to-gate spacing to be smaller to increase the cell density and reduce the Vf.
[0068] FIG. 11 illustrates another design of the p+ region 62 of a pull-down p-channel MOSFET relative to the n+ source 64. FIG. 12 is taken across line 12-12 in FIG. 11, and FIG. 13 is taken across line 13-13 in FIG. 11. In this embodiment, the relative size of the n+ source 64 is increased for improved Vf, yet the contact opening 66 for the cathode metal can be very narrow, allowing smaller gate-to-gate spacing for improved Vf. The p+ region 62 has horizontal fingers that extend into the n+ source 62, where the horizontal fingers are contacted by the cathode metal. As in FIGS. 9 and 10, the layers below the p-well 14 are not shown but may be similar to those layers in FIG. 1 or layers for forming an IGBT.
[0069] FIGS. 12 and 13 illustrate that the p+ region 62 does not extend along the wall of one of the opposing gates 12, and the n+ source 64 does not extend along the wall of the other one of the gates 12. In this embodiment, the percentage area of the p+ region 62 is about 50% of the top area between the gates 12. Since the n+ source 64 is relatively large and next to one of the gate walls, there is very low on-resistance, since electrons injected by the n+ source 64 do not need to flow horizontally through the higher resistance n layer 30. The n layer 30 along the gate wall is highly conductive when the IGTO device is on. As a result, the Vf, and turn-off time are very low.
[0070] FIGS. 14-16 illustrate an embodiment of an IGTO device that includes a pull-down p-channel MOSFET, where the n layer 30 in FIGS. 1, 9, and 12 is not formed below the n+ source 70. FIG. 15 is taken across line 15-15 in FIG. 14, and FIG. 16 is taken across line 16-16 in FIG. 14. In FIGS. 14-16, the n layer 72 is only formed below the p+ region 74 and connects to the n+ source 70. Since the n+ source 70 extends to the gate wall, there is a very low resistance path from the n+ source 70 to below the gate 12, due to the inversion of the p-well 14 next to the gate 12. The narrow contact opening 66 is similar to that shown in FIG. 11 so the gate-to-gate spacing may be small (e.g., less than 1.5 microns).
[0071] FIG. 17 is a top down view of a portion of two cells between opposing gates 12 in an IGTO device having a pull-down p-channel MOSFET. The gates 12 are within trenches formed as a rectangular mesh of trenches. The rectangular cells will typically be elongated, and the horizontal regions of the gates 12 are not shown. The narrow rectangular contact openings 76 in a dielectric layer 78 (FIG. 18) over the gates 12 and over a portion of the semiconductor are shown. The cathode metal (not shown) overlies the dielectric 78 and directly contacts the exposed semiconductor surface.
[0072] The p+ regions 80 and n+ sources 82 are formed in strips perpendicular to the long edge of the rectangular cells. FIG. 18 is a cross-section along line 18-18 in FIG. 17; FIG. 19 is a cross-section along line 19-19 in FIG. 17; and FIG. 20 is a cross-section along line 20-20 in FIG. 17.
[0073] The contact opening 76 can be made any width, while still allowing the cathode metal to contact all the rows of the p+ regions 80 and the n+ sources 82, to optimize the gate-to-gate spacing for optimizing Vf and turn-off time.
[0074] In another embodiment, there is only a single row of the p+ region 80 per cell to increase the n+ source 82 area per cell.
[0075] FIGS. 21-24 are process flow cross-sections across a single cell in an IGTO device to illustrate a technique to form a self-aligned cathode metal without having to form a contact opening. So there is a savings in not having to form an extra dielectric layer, aligning a contact opening mask, and then etching the contact opening. This basic process may be used to form the various IGTO devices described herein.
[0076] In FIG. 21, an n-type epitaxial (epi) layer 84, forming the layers 26 and 28 in FIG. 1 and in the other embodiments, is grown over a p+ substrate (e.g., substrate 34 in FIG. 1). An oxide layer 86 is formed over the surface of the n-type epi layer 84. A silicon nitride layer 88 is then deposited over the oxide layer 86. The layers 86 and 88 are then masked and etched to expose a trench area for the gates. The trenches 90 are then etched using reactive ion etching (RIE).
[0077] In FIG. 22, a thin gate oxide 16 is thermally grown over the sidewalls of the trench 90. Doped polysilicon is then deposited in the insulated trenches to form the conductive gate 12.
[0078] Excess polysilicon is etched away. The top of the polysilicon is then oxidized to form a relatively thick oxide layer 92 over the gate 12 so the gate 12 potential will not be affected by the cathode metal voltage. The silicon nitride layer 88 is then etched away.
[0079] In FIG. 23, an implant step implants p-type boron ions into the n-epi layer 84 to form the p-well 14. The boron dopant is then diffused. Another implant step implants n-type phosphorus ions into the surface of the n-type epi layer 84 to form the n layer 30. The phosphorus atoms are then diffused. The surface is masked, and boron is implanted and diffused (by annealing) to form the p+ regions 94 for the pull-down MOSFET. The p+ region 94 configuration may be like any of those previously described. The surface is then masked, and arsenic is implanted and diffused (by annealing) to form the n+ source 96.
[0080] In FIG. 24, a blanket etch is performed to expose the semiconductor surface between the gates 12. The cathode metal 22 is then deposited and etched. The cathode metal 22 contacts the p+ region 94 and the n+ region 96. As seen, no contact opening mask and etch are required in this area since the oxide 92 over the gate 12 is initially thick and can be etched back during the blanket etch that exposes the active area between the gates 12. A mask and etch may be required to connect a metal gate electrode to the gate polysilicon.
[0081] FIGS. 25-32 are directed to a technique to adjust the Vth of the pull-down p-channel MOSFET, including forming a depletion mode pull-down MOSFET, using a novel angled boron implant into the sidewalls of the trenches. Adjusting the Vth can be used to customize the gate turn-off voltage of the IGTO device.
[0082] FIG. 25 is similar to FIG. 1 except that a depletion mode pull-down MOSFET is formed, rather than an enhancement mode pull-down MOSFET. A depletion mode MOSFET conducts current when there is a zero gate-source voltage, since the channel 98 between the p-well 14 and the p+ region 94 is p-type. Therefore, the channel of the depletion mode pull-down MOSFET conducts at a zero gate voltage when the IGTO device is off. When the gate voltage is positive and above the threshold voltage of the IGTO device (the device is on), the depletion mode pull-down MOSFET is turned off so has no effect. By simply taking the gate voltage to zero volts, the pull-down MOSFET conducts to turn off the vertical NPN transistor and quickly remove carriers from the p-well 14. Accordingly, no negative voltage generator is needed to generate the negative voltage that is needed to turn off the enhancement mode pull-down MOSFET of prior art FIG. 1.
[0083] FIG. 26 is a cross-section of an empty trench 102 formed in an n-type epi layer 104, such as the n-type epi layer 84 of FIG. 21. The gate oxide 16 may or may not be present. Boron 106 is then implanted at an angle relative to the vertical sidewalls of the trench 102, using the edge of the trench 102 to block the boron 106 from being implanted below a certain level of the trench 102. An implant dose of 10e12-5e14 is used in one embodiment. For the angled implant, the wafer may be angled with respect to the boron source. The angle determines the length of the p-channel in a depletion mode MOSFET. Both sidewalls of the trench 102 may be subjected to separate angled implants. The boron 106 is then diffused by an anneal step to activate the dopants.
[0084] FIG. 27 illustrates the formation of the resulting narrow p region 108 that will be the channel of the depletion mode pull-down MOSFET.
[0085] In FIG. 28, the gate oxide layer 16 (if not already formed), the polysilicon gate 12, n-epi layer 28, the p-well 14, n layer 30, n+ source 96, p+ region 94, and oxide 92 are then formed, as described with respect to FIGS. 21-24. The p region 108 forms the channel in the pull-down MOSFET between the p-well 14 and the p+ region 94. A cathode metal is then formed over the surface, as in FIG. 24. FIG. 28 shows a version of the device in which the boron is implanted along only one trench sidewall to form the p region 108.
[0086] FIG. 29 illustrates one possible top down view of the active area in FIG. 28, showing the p+ region 94 having fingers that extend into the n+ source 96. In such an embodiment, the boron is angle-implanted into only one sidewall of the trench 102.
[0087] FIG. 30 illustrates another embodiment of a top down view of the active area in FIG. 28 showing the p+ region 110 and n+ source 112.
[0088] FIG. 31 illustrates the angled implantation of boron 106 into both sidewalls of the trench 102 to change the Vth of the pull-down p-channel MOSFET or to form a depletion mode pull-down MOSFET on both sides of a cell for improved turn-off time.
[0089] FIG. 32 illustrates one possible top down view of the active area of an IGTO device having the depletion mode pull-down MOSFET on both sides of a cell, formed using the dual angled implants of FIG. 31. The p+ regions 114 and 116 are along the gates, and the n+ source 118 is in the middle. A cathode metal will overlie some portions of the p+ regions 114 and 116 and the n+ source 118.
[0090] The angled-implantation technique for forming a depletion mode MOSFET, whether n-channel or p-channel, can be used to form a vertical depletion mode MOSFET in any structure, whether or not the depletion mode MOSFET is used for turning off a device. An angled implant of arsenic into sidewalls of a trench would be used to form a depletion mode n-channel MOSFET.
[0091] FIGS. 33-35 relate to forming a non-self-aligned contact opening for a cathode metal, where the p+ region for the pull-down MOSFET is a single horizontal strip.
[0092] FIG. 33 is a top down view of the active area of an IGTO device cell, showing the n+ sources 120 and 122 and the p+ region 124 formed as a horizontal strip. The aligned contact opening 126 in a dielectric layer 128 (FIG. 34) allows the cathode metal to contact the n+ sources 120 and 122 and the p+ region 124. The contact opening 126 can be made very narrow to allow small gate-to-gate spacings.
[0093] FIG. 34 is taken along line 34-34 in FIG. 33, and FIG. 35 is taken along line 35-35 in FIG. 33.
[0094] FIGS. 36-38 relate to forming a self-aligned contact opening for a cathode metal, where the p+ region for the pull-down MOSFET is a single horizontal strip.
[0095] FIG. 36 is a top down view of the active area of an IGTO device cell, showing the n+ sources 130 and 132 and the p+ region 134 formed as a horizontal strip.
[0096] FIG. 37 is taken along line 37-37 in FIG. 36, and FIG. 38 is taken along line 38-38 in FIG. 36.
[0097] After the trench is formed and filled with polysilicon to form the gate 12, a relatively thick oxide 136 is grown over the polysilicon. A blanket etch removes any thin dielectric over the active area. The resulting exposed area between the gates 12 can then be contacted with a cathode metal layer without requiring the formation of a contact opening, thus saving a few process steps. This is similar to the process shown in FIGS. 21-24.
[0098] FIG. 39 is a top down view of an array of four cells. The gates 138 are formed in trenches forming a rectangular mesh. Each cell includes the gates 138 (forming a mesh), and three n+ sources 140, 142, and 144, formed as horizontal strips. Each cell also includes p+ regions 146 and 148 between the n+ sources 140, 142, and 144. A contact opening 150 for the cathode metal contacts the n+ sources 140, 142, and 144 and the p+ regions 146 and 148. Only a small portion of the cell is taken up by the p+ regions 146 and 148, resulting in a low Vf. The p+ regions 146 and 148 along the gate walls may be the top regions of a pull-down MOSFET in each cell for turning off the cell. The gates 138 form fingers that extend into each cell to greatly add to the gate surface area to improve efficiency and Vf. The n+ sources 140, 142, and 144 are relatively long and narrow and are virtually surrounded by the gate 138, except for the p+ region areas, so there is low on-resistance. The small area of the pull-down MOSFET is sufficient to greatly reduce the turn-off time.
[0099] FIG. 40 is a top down view of a cell of an IGTO device, where the gate 152 and the n+ source 154 have interdigitated fingers for abutting along a very large surface area for high efficiency and low Vf. The p+ regions 156 are portions of pull-down MOSFET devices for rapidly turning off the device. A contact opening 160 allows the cathode metal to contact the n+ source 154 and p+ regions 156. This concept of interdigitated fingers and the integrated pull-down MOSFET can be applied to other types of MOS-gated devices.
[0100] Any features described herein can be combined together and can be incorporated in more than one type of trench, MOS-gated power device.
[0101] The polarities of the various semiconductor regions may be reversed, depending on whether the top electrode is to be a cathode or an anode.
[0102] While particular embodiments of the present invention have been shown and described, it will be obvious to those skilled in the art that changes and modifications may be made without departing from this invention in its broader aspects and, therefore, the appended claims are to encompass within their scope all such changes and modifications as fall within the true spirit and scope of this invention.
