Patent classifications
H01L21/285
LINER FOR V-NAND WORD LINE STACK
Methods of forming memory structures are discussed. Specifically, methods of forming 3D NAND devices are discussed. Some embodiments form memory structures with a metal nitride barrier layer, an α-tungsten layer, and a bulk metal material. The barrier layer comprises a TiXN or TaXN material, where X comprises a metal selected from one or more of aluminum (Al), silicon (Si), tungsten (W), lanthanum (La), yttrium (Yt), strontium (Sr), or magnesium (Mg).
METHOD OF FORMING AN ELECTRONIC STRUCTURE USING REFORMING GAS, SYSTEM FOR PERFORMING THE METHOD, AND STRUCTURE FORMED USING THE METHOD
Methods of and systems for reforming films comprising silicon nitride are disclosed. Exemplary methods include providing a substrate within a reaction chamber, forming activated species by irradiating a reforming gas with microwave radiation, and exposing substrate to the activated species. A pressure within the reaction chamber during the step of forming activated species can be less than 50 Pa.
Integrated Assemblies Having Metal-Containing Liners Along Bottoms of Trenches, and Methods of Forming Integrated Assemblies
Some embodiments include methods of forming integrated assemblies. A conductive structure is formed to include a semiconductor-containing material over a metal-containing material. An opening is formed to extend into the conductive structure. A conductive material is formed along a bottom of the opening. A stack of alternating first and second materials is formed over the conductive structure either before or after forming the conductive material. Insulative material and/or channel material is formed to extend through the stack to contact the conductive material. Some embodiments include integrated assemblies.
RF grounding configuration for pedestals
Embodiments of the present disclosure generally relate to substrate supports for process chambers and RF grounding configurations for use therewith. Methods of grounding RF current are also described. A chamber body at least partially defines a process volume therein. A first electrode is disposed in the process volume. A pedestal is disposed opposite the first electrode. A second electrode is disposed in the pedestal. An RF filter is coupled to the second electrode through a conductive rod. The RF filter includes a first capacitor coupled to the conductive rod and to ground. The RF filter also includes a first inductor coupled to a feedthrough box. The feedthrough box includes a second capacitor and a second inductor coupled in series. A direct current (DC) power supply for the second electrode is coupled between the second capacitor and the second inductor.
Method for manufacturing a semiconductor device
The present disclosure a method for manufacturing a metal-oxide-semiconductor (MOS) transistor device. The method includes steps of providing a substrate; forming a gate electrode over the substrate; forming a source region and a drain region in the substrate; depositing an isolating layer over the substrate and the gate electrode; forming a plurality of contact holes in the isolating layer to expose the gate electrode, the source region, and the drain region; forming a plurality of metal contacts in the gate electrode, the source region, and the drain region; depositing a contact liner in the contact holes; and depositing a conductive material in the contact holes, wherein the conductive material is surrounded by the contact liner.
Method of forming metal contact for semiconductor device
A semiconductor device includes a first semiconductor fin, a first epitaxial layer, a first alloy layer and a contact plug. The first semiconductor fin is on a substrate. The first epitaxial layer is on the first semiconductor fin. The first alloy layer is on the first epitaxial layer. The first alloy layer is made of one or more Group IV elements and one or more metal elements, and the first alloy layer comprises a first sidewall and a second sidewall extending downwardly from a bottom of the first sidewall along a direction non-parallel to the first sidewall. The contact plug is in contact with the first and second sidewalls of the first alloy layer.
Aluminum-based gallium nitride integrated circuits
Gallium nitride-based monolithic microwave integrated circuits (MMICs) can comprise aluminum-based metals. Electrical contacts for gates, sources, and drains of transistors can include aluminum-containing metallic materials. Additionally, connectors, inductors, and interconnect devices can also comprise aluminum-based metals. The gallium-based MMICs can be manufactured in complementary metal oxide semiconductor (CMOS) facilities with equipment that produces silicon-based semiconductor devices.
Semiconductor device having improved electrostatic discharge protection
Various embodiments of the present disclosure are directed towards a semiconductor device. The semiconductor device comprises a source region and a drain region in a substrate and laterally spaced. A gate stack is over the substrate and between the source region and the drain region. The drain region includes two or more first doped regions having a first doping type in the substrate. The drain region further includes one or more second doped regions in the substrate. The first doped regions have a greater concentration of first doping type dopants than the second doped regions, and each of the second doped regions is disposed laterally between two neighboring first doped regions.
Conditioning treatment for ALD productivity
Deposition methods and apparatus for conditioning a process kit to increase process kit lifetime are described. A nitride film formed on a process kit is exposed to conditioning process comprising nitrogen and hydrogen radicals to condition the nitride film to decrease particulate contamination from the process kit.
SUBSTRATE TREATMENT APPARATUS AND SEMICONDUCTOR DEVICE MANUFACTURING METHOD USING THE SAME
A semiconductor device manufacturing method comprising loading a substrate into a substrate treatment apparatus, performing a deposition process on the substrate, and cleaning the substrate treatment apparatus. The substrate treatment apparatus includes a housing defining a treatment area in which the deposition process is performed, a gas supply supplying a first process gas at a flow rate of 1000 sccm to 15000 sccm and supplying a second process gas, a remote plasma supply connected to the gas supply, generating a first process plasma and a second process plasma by applying RF power to plasma-process the first process gas and the second process gas, and a shower head installed in the housing to supply the first process plasma and the second process plasma to the treatment area. The second process plasma cleans a membrane material deposited on an inner wall of the housing.