H01L21/288

PROCESS OF FORMING SEMICONDUCTOR DEVICE HAVING INTERCONNECTION FORMED BY ELECTRO-PLATING

A process of forming a semiconductor device that includes an interconnection formed by electro-plating is disclosed. The process comprises steps of: forming a stopper layer on the first insulating film; covering the stopper layer and the first insulating film with a second insulating film; preparing a first mask having an edge that overlaps with the stopper layer; depositing a seed layer on the first mask and the second insulating film that is exposed from the first mask; preparing a second mask having an edge that overlaps with the stopper layer, the edge of the first mask retreating from the edge of the second mask; forming an upper layer on the seed layer by electro-plating a metal so as not to overlap with the first mask; and removing the seed layer exposed from the upper layer by etching.

GRAPHENE-SUPPORTED NOBLE-METAL COMPOSITE POWDER AND PREPARATION METHOD THEREOF, AND SCHOTTKY DEVICE

Disclosed are a graphene-supported noble-metal composite powder, a preparation method thereof, and a Schottky device. In the disclosure, graphene oxide and a noble metal precursor, as raw materials, are subjected to a hydrothermal reduction reaction to prepare the composite powder. In the process of the hydrothermal reduction reaction, graphene oxide and noble metal ions can be simultaneously reduced, and the formed noble metal nanoparticles are uniformly distributed on the surface and between layers of graphene, which effectively suppresses agglomeration of graphene, thereby fully exerting the electrical conductivity of graphene.

GRAPHENE-SUPPORTED NOBLE-METAL COMPOSITE POWDER AND PREPARATION METHOD THEREOF, AND SCHOTTKY DEVICE

Disclosed are a graphene-supported noble-metal composite powder, a preparation method thereof, and a Schottky device. In the disclosure, graphene oxide and a noble metal precursor, as raw materials, are subjected to a hydrothermal reduction reaction to prepare the composite powder. In the process of the hydrothermal reduction reaction, graphene oxide and noble metal ions can be simultaneously reduced, and the formed noble metal nanoparticles are uniformly distributed on the surface and between layers of graphene, which effectively suppresses agglomeration of graphene, thereby fully exerting the electrical conductivity of graphene.

Waterproof electronic device and manufacturing method thereof

A waterproof electronic device includes: an electronic component module having an electronic component including a semiconductor element, a heat dissipating member provided on the electronic component in a thermally conductive manner, and an insulating material that surrounds the electronic component in such a manner that one surface of the heat dissipating member is exposed; and a waterproof film that is formed at least on whole surfaces in regions of the electronic component module that are to be immersed in a coolant.

Regulation plate, anode holder, and substrate holder
11686009 · 2023-06-27 · ·

To partially or locally control a plating film thickness on a polygonal substrate. There is provided a regulation plate for adjusting a current between an anode and the polygonal substrate. This regulation plate includes a main body that has an edge forming a polygonal opening through which the current passes and an attachable/detachable shielding member to shield at least a part of the polygonal opening.

METHOD OF MANUFACTURING ELECTROFORMED COMPONENTS

In manufacturing of a first electroformed component and a second electroformed component having portions fitted to each other into close contact, after the first electroformed component is formed, the first electroformed component is used as a portion of an electroforming mold to form the second electroformed component. Using the first electroformed component as a portion of the electroforming mold to form the second electroformed component, the shape of the first electroformed component is transferred to the second electroformed component. As a result, multiple types of components differing in shape may be accurately manufactured concurrently in a series of manufacturing steps.

Plated lead frame including doped silver layer

A lead frame comprises a substrate comprising copper and includes a layer of bright silver is plated onto the substrate. A layer of doped bright silver is thereafter plated over a top surface of the layer of bright silver for enhancing the performance of LED devices utilizing the lead frame.

ELECTRODE MATERIAL FOR ORGANIC SEMICONDUCTOR DEVICE
20170358765 · 2017-12-14 · ·

An object of the present invention is to provide an electrode material for an organic semiconductor device which maintains excellent conductivity and of which contact properties with an organic semiconductor becomes favorable. The electrode material for an organic semiconductor device of the present invention contains inorganic nanoparticles and an organic π-conjugated ligand, in which the organic π-conjugated ligand is a ligand having at least one electron-withdrawing substituent.

METHOD OF MAKING A SEMICONDUCTOR DEVICE AND SEMICONDUCTOR DEVICE
20220384253 · 2022-12-01 ·

A method includes depositing a metallic hardmask over a dielectric layer. The method further includes etching a metallic hardmask opening in the metallic hardmask to expose a top surface of the dielectric layer. The method further includes modifying a sidewall of the metallic hardmask opening by adding non-metal atoms into the metallic hardmask. The method further includes depositing a conductive material in the metallic hardmask opening.

INTERCONNECT STRUCTURE AND SEMICONDUCTOR DEVICE HAVING THE SAME

Provided is an interconnect structure including: a first conductive feature, disposed in a first dielectric layer; a second conductive feature, disposed over the first conductive feature and the first dielectric layer; a via, disposed between the first and second conductive features and being in direct contact with the first and second conductive features; and a barrier structure, lining a sidewall and a portion of a bottom surface of the second conductive feature, a sidewall of the via, a portion of a top surface of the first conductive feature, and a top surface of the first dielectric layer.