Exemplary methods of electroplating may include providing a patterned substrate having at least one opening, where the opening includes one or more sidewalls and a bottom surface. The methods may also include plating a first portion of ruthenium-containing material on the bottom surface of the opening at a first deposition rate and a second portion of ruthenium-containing material on the sidewalls of the opening at a second deposition rate, where the first deposition rate is greater than the second deposition rate. The methods may be used to make integrated circuit devices that include void-free, electrically-conductive lines and columns of ruthenium-containing materials.

Exemplary methods of electroplating include contacting a patterned substrate with a plating bath in an electroplating chamber, where the pattern substrate includes at least one opening having a bottom surface and one or more sidewall surfaces. The methods may further include forming a nanotwin-containing metal material in the at least one opening. The metal material may be formed by two or more cycles that include delivering a forward current from a power supply through the plating bath of the electroplating chamber for a first period of time, plating a first amount of the metal on the bottom surface of the opening on the patterned substrate and a second amount of the metal on the sidewall surfaces of the opening, and delivering a reverse current from the power supply through the plating bath of the electroplating chamber to remove some of the metal plated in the opening on the patterned substrate.

Exemplary methods of electroplating may include providing a patterned substrate having at least one opening, where the opening includes one or more sidewalls and a bottom surface. The methods may also include plating a first portion of ruthenium-containing material on the bottom surface of the opening at a first deposition rate and a second portion of ruthenium-containing material on the sidewalls of the opening at a second deposition rate, where the first deposition rate is greater than the second deposition rate. The methods may be used to make integrated circuit devices that include void-free, electrically-conductive lines and columns of ruthenium-containing materials.

In an embodiment, a device includes: a molding compound; an integrated circuit die encapsulated in the molding compound; a through via adjacent the integrated circuit die; and a redistribution structure over the integrated circuit die, the molding compound, and the through via, the redistribution structure electrically connected to the integrated circuit die and the through via, the redistribution structure including: a first dielectric layer disposed over the molding compound; a first conductive via extending through the first dielectric layer; a second dielectric layer disposed over the first dielectric layer and the first conductive via; and a second conductive via extending through the second dielectric layer and into a portion of the first conductive via, an interface between the first conductive via and the second conductive via being non-planar.

According to one embodiment, there is provided a method for manufacturing a semiconductor device. The method includes metal electroplating on a surface of a first electrode formed on a first surface of a semiconductor substrate with a plating solution which contains aggregates of a supercritical fluid and a solution of a plating metal ion and an electrolyte. The first surface includes a recess. The surface is along with a shape of the recess. The recess has a first dimension and a second dimension, and assuming that an aspect ratio of the recess is given as a ratio of the second dimension to the first dimension, a median of a particle size distribution of the aggregates is greater than the first dimension.

A manufacturing method of a metal grid includes: providing a base substrate; forming a pattern including a first dielectric layer on the base substrate through a patterning process such that the first dielectric layer has a first groove in a lattice shape; forming a second dielectric layer on a side of the first dielectric layer away from the base substrate such that the second dielectric layer is deposited at least on a sidewall of the first groove to form a second groove in a lattice shape; and forming a metal material in the second groove, and removing at least a part of a material of the second dielectric layer such that an orthographic projection of the part of the material of the second dielectric layer on the base substrate does not overlap with an orthographic projection of the metal material on the base substrate, to form a metal grid.

A manufacturing method of a metal grid includes: providing a base substrate; forming a pattern including a first dielectric layer on the base substrate through a patterning process such that the first dielectric layer has a first groove in a lattice shape; forming a second dielectric layer on a side of the first dielectric layer away from the base substrate such that the second dielectric layer is deposited at least on a sidewall of the first groove to form a second groove in a lattice shape; and forming a metal material in the second groove, and removing at least a part of a material of the second dielectric layer such that an orthographic projection of the part of the material of the second dielectric layer on the base substrate does not overlap with an orthographic projection of the metal material on the base substrate, to form a metal grid.

Exemplary methods of electroplating a metal with a nanotwin crystal structure are described. The methods may include plating a metal material into at least one opening on a patterned substrate, where at least a portion of the metal material is characterized by a nanotwin crystal structure. The methods may further include polishing an exposed surface of the metal material in the opening to reduce an average surface roughness of the exposed surface to less than or about 1 nm. The polished exposed surface may include at least a portion of the metal material characterized by the nanotwin crystal structure. In additional examples, the nanotwin-phased metal may be nanotwin-phased copper.

Embodiments include plating a contact feature in a first opening in a mask layer, the contact feature physically coupled to a contact pad, the contact feature partially filling the first opening. A solder cap is directly plated onto the contact feature in the first opening. The mask layer is then removed to expose an upper surface of a work piece, the contact feature vertically protruding from the work piece. After utilizing the solder cap, etching the solder cap to remove the solder cap from over the contact feature. A first encapsulant is deposited laterally around and over an upper surface of the contact feature. The first encapsulant is planarized to level an upper surface of the first encapsulant with the upper surface of the contact feature.

Embodiments include plating a contact feature in a first opening in a mask layer, the contact feature physically coupled to a contact pad, the contact feature partially filling the first opening. A solder cap is directly plated onto the contact feature in the first opening. The mask layer is then removed to expose an upper surface of a work piece, the contact feature vertically protruding from the work piece. After utilizing the solder cap, etching the solder cap to remove the solder cap from over the contact feature. A first encapsulant is deposited laterally around and over an upper surface of the contact feature. The first encapsulant is planarized to level an upper surface of the first encapsulant with the upper surface of the contact feature.