A method includes forming a semiconductor fin protruding higher than top surfaces of isolation regions. The isolation regions extend into a semiconductor substrate. The method further includes etching a portion of the semiconductor fin to form a trench, filling the trench with a first dielectric material, wherein the first dielectric material has a first bandgap, and performing a recessing process to recess the first dielectric material. A recess is formed between opposing portions of the isolation regions. The recess is filled with a second dielectric material. The first dielectric material and the second dielectric material in combination form an additional isolation region. The second dielectric material has a second bandgap smaller than the first bandgap.

A method for manufacturing a semiconductor feature includes: alternatingly forming first and second dielectric layers on a semiconductor substrate along a vertical direction; forming multiple spaced-apart trenches penetrating the first and second dielectric layers; forming multiple support segments filling the trenches; removing the second dielectric layers to form multiple spaces; forming multiple conductive layers filling the spaces; removing the support segments to expose the conductive layers and the first dielectric layers; selectively forming a blocking layer covering the first dielectric layers outside of the conductive layers; forming multiple selectively-deposited sub-layers on the exposed conductive layers outside of the blocking layer and each connected to one of the conductive layers; forming multiple channel sub-layers on the selectively-deposited sub-layers outside of the blocking layer; removing the blocking layer; forming multiple isolation sub-layers filling the trenches; and forming multiple source/drain segments each connected to corresponding ones of the channel sub-layers.

A method for manufacturing a semiconductor device is provided. The method includes a step of performing a chemical mechanical polishing process on a first silicon oxide layer to form a planar surface layer; surface treatment is performed on the planar surface layer to form a treated planarization layer, and a second silicon oxide layer is formed on the treated planarization layer.

The present application discloses a semiconductor device with stacked dies and the method for fabricating the semiconductor device with the stacked dies. The semiconductor device includes a first semiconductor die including a first substrate including a first and a second region, a first circuit layer on the first substrate, a control circuit on the first region and in the first circuit layer; and through die vias along the first circuit layer and the second region; a second semiconductor die stacked on the first semiconductor die and including second conductive pads connected to the through die vias and the control circuit; and a third semiconductor die stacked under the first semiconductor die and including third conductive pads connected to the through die vias and the control circuit. The through die vias, the second conductive pads, and the third conductive pads configure transmission channels through which the control circuit is capable to access the second and the third semiconductor die.

Methods and apparatus for forming a barrier layer are provided herein. In some embodiments, a method of forming a barrier layer on a substrate includes treating an exposed layer deposited on a substrate and within a feature of the substrate by pulsing a bias power applied to a substrate support supporting the substrate while exposing the layer to a plasma. The exposed layer can be deposited by an atomic layer deposition process, and can be, for example, a tantalum nitride layer. The bias power can be up to 500 watts of RF power at a pulse frequency of about 1 Hz to about 10 kHz. The bias power can be pulsed uniformly or at multiple different levels.

A planarization apparatus, including a chuck having a first surface and a second surface at two opposing sides thereof. The chuck includes a first zone extending along a periphery of the chuck, a second zone at an inner portion of the chuck, the second zone being surrounded by the first zone; and a flexure connecting the first zone with the second zone. The first zone includes a first member extending along the first surface from the flexure and a first ring land protruding from the first member adjacent to the flexure.

To provide modified colloidal silica capable of improving the stability of the polishing speed with time when used as abrasive grains in a polishing composition for polishing a polishing object that contains a material to which charged modified colloidal silica easily adheres, such as a SiN wafer, and to provide a method for producing the modified colloidal silica. Modified colloidal silica, being obtained by modifying raw colloidal silica, wherein the raw colloidal silica has a number distribution ratio of 10% or less of microparticles having a particle size of 40% or less relative to a volume average particle size based on Heywood diameter (equivalent circle diameter) as determined by image analysis using a scanning electron microscope.

Methods and systems for selectively depositing dielectric films on a first surface of a substrate relative to a passivation layer previously deposited on a second surface are provided. The methods can include at least one cyclical deposition process used to deposit material on the first surface while the passivation layer is removed, thereby preventing deposition over the passivation layer.

An object of the present invention is to provide: a compound containing an imide group which is not only cured under film formation conditions of inert gas as well as air and has excellent heat resistance and properties of filling and planarizing a pattern formed on a substrate, but can also form an organic underlayer film with favorable adhesion to a substrate, and a material for forming an organic film containing the compound. A material for forming an organic film, including: (A) a compound for forming an organic film shown by the following general formula (1A); and (B) an organic solvent, ##STR00001## noting that in the general formula (1B), when W.sub.1 represents ##STR00002##  R.sub.1 does not represent any of ##STR00003##

In a method of manufacturing a semiconductor device, a first interlayer dielectric (ILD) layer is formed over a substrate, a CMP stop layer is formed over the first ILD layer, a trench opening is formed by patterning the CMP stop layer and the first ILD layer, an underlying first process mark is formed by forming a first conductive layer in the trench opening, a lower dielectric layer is formed over the underlying first process mark, a middle dielectric layer is formed over the lower dielectric layer, an upper dielectric layer is formed over the middle dielectric layer, a planarization operation is performed on the upper, middle and lower dielectric layers so that a part of the middle dielectric layer remains over the underlying first process mark, and a second process mark by the lower dielectric layer is formed by removing the remaining part of the middle dielectric layer.