FCVD using multi-step anneal treatment and devices thereof are disclosed. In an embodiment, a method includes depositing a flowable dielectric film on a substrate. The flowable dielectric film is deposited between a first semiconductor fin and a second semiconductor fin. The method further includes annealing the flowable dielectric film at a first anneal temperature for at least 5 hours to form a first dielectric film, annealing the first dielectric film at a second anneal temperature higher than the first anneal temperature to form a second dielectric film, annealing the second dielectric film at a third anneal temperature higher than the first anneal temperature to form an insulating layer, applying a planarization process to the insulating layer, and etching the insulating layer to STI regions on the substrate.

FCVD using multi-step anneal treatment and devices thereof are disclosed. In an embodiment, a method includes depositing a flowable dielectric film on a substrate. The flowable dielectric film is deposited between a first semiconductor fin and a second semiconductor fin. The method further includes annealing the flowable dielectric film at a first anneal temperature for at least 5 hours to form a first dielectric film, annealing the first dielectric film at a second anneal temperature higher than the first anneal temperature to form a second dielectric film, annealing the second dielectric film at a third anneal temperature higher than the first anneal temperature to form an insulating layer, applying a planarization process to the insulating layer, and etching the insulating layer to STI regions on the substrate.

The present disclosure relates to a semiconductor structure and a manufacturing method thereof. The manufacturing method of a semiconductor structure includes: providing a substrate, where a plurality of contact pads are formed on the substrate; depositing a dielectric layer on the substrate, where the dielectric layer fills gaps between the contact pads and covers the contact pads; and etching the dielectric layer through a plasma etching process to expose the contact pads, where an etching gas used in the plasma etching process includes an oxygen-free etching gas. The manufacturing method can avoid the formation of metal oxides on the contact pads, and avoid residual conductive metal particles or metal compounds on surfaces of the contact pads and the adjacent dielectric layers, which is beneficial to ensure the electrical performance of the semiconductor structure, thereby improving the use reliability of the semiconductor structure.

Methods process microelectronic workpieces with inverse extreme ultraviolet (EUV) patterning processes. In part, the inverse patterning techniques are applied to reduce or eliminate defects experienced with conventional EUV patterning processes. The inverse patterning techniques include additional process steps as compared to the conventional EUV patterning processes, such as an overcoat process, an etch back or planarization process, and a pattern removal process. In addition, further example embodiments combine inverse patterning techniques with line smoothing treatments to reduce pattern roughness and achieve a target level of line roughness. By using this additional technique, line pattern roughness can be significantly improved in addition to reducing or eliminating microbridge and/or other defects.

A semiconductor structure includes a molding, a device in the molding, and a RDL over the device and the molding. The RDL includes a first portion directly over a surface of the molding, and a second portion directly over a surface of the device. A bottom surface of the first portion is in contact with the surface of the molding, and a bottom surface of the second portion is in contact with the surface of the device. The bottom surface of the first portion of the RDL and the bottom surface of the second portion of the RDL are at different levels and misaligned from each other. A thickness of the first portion is greater than a thickness of the second portion.

Embodiments of the present disclosure generally relate to techniques for deposition of high-density films for patterning applications. In one embodiment, a method of processing a substrate is provided. The method includes depositing a carbon hardmask over a film stack formed on a substrate, wherein the substrate is positioned on an electrostatic chuck disposed in a process chamber, implanting ions into the carbon hardmask, wherein depositing the carbon hardmask and implanting ions into the carbon hardmask are performed in the same process chamber, and repeating depositing the carbon hardmask and implanting ions into the carbon hardmask in a cyclic fashion until a pre-determined thickness of the carbon hardmask is reached.

Embodiments of the present disclosure generally relate to techniques for deposition of high-density films for patterning applications. In one embodiment, a method of processing a substrate is provided. The method includes depositing a carbon hardmask over a film stack formed on a substrate, wherein the substrate is positioned on an electrostatic chuck disposed in a process chamber, implanting ions into the carbon hardmask, wherein depositing the carbon hardmask and implanting ions into the carbon hardmask are performed in the same process chamber, and repeating depositing the carbon hardmask and implanting ions into the carbon hardmask in a cyclic fashion until a pre-determined thickness of the carbon hardmask is reached.

A method of fabricating a hollow wall for controlling directional deposition of material comprises: forming a layer of resist on a substrate; removing a portion of the resist selectively to form a channel in the resist; forming a layer of an amorphous dielectric material in the channel; and removing the resist to form the hollow wall. The channel has a front surface configured to prevent bending of a corresponding front face of the hollow wall. The hollow wall is useful for controlling deposition of material when fabricating semiconductor-superconductor hybrid devices, for example. By configuring the channel appropriately, bending of the hollow wall can be prevented, allowing for more precise deposition of material. Also provided is a further method of fabricating a hollow wall; and a method of fabricating a device using the hollow walls.

A manufacturing method of a semiconductor structure includes at least the following steps. A patterned mask layer with a first opening is formed on a dielectric layer overlying a semiconductor substrate. A portion of the dielectric layer accessibly exposed by the first opening of the patterned mask layer is removed to form a second opening. A first protective film is formed on inner sidewalls of the dielectric layer and the patterned mask layer, where the second opening and the first protective film are formed at the same step. A second protective film is formed on the first protective film to form a protective structure covering the inner sidewalls. A portion of the semiconductor substrate accessibly exposed by the second opening is removed to form a via hole including an undercut underlying the protective structure. The via hole is trimmed and a through substrate via is formed in the via hole.

A control gate electrode and a memory gate electrode of a memory cell of a non-volatile memory are formed in a memory cell region of a semiconductor substrate, and a dummy gate electrode is formed in a peripheral circuit region. Then, n.sup.+-type semiconductor regions for a source or a drain of the memory cell are formed in the memory cell region and n.sup.+-type semiconductor regions for a source or a drain of MISFET are formed in the peripheral circuit region. Then, a metal silicide layer is formed over the n.sup.+-type semiconductor regions but the metal silicide layer is not formed over the control gate electrode, the memory gate electrode, and the gate electrode. Subsequently, the gate electrode is removed and replaced with the gate electrode for MISFET, Then, after removing the gate electrode and replacing it with a gate electrode for MISFET, a metal silicide layer is formed over the memory gate electrode and the control gate electrode.