A semiconductor device includes a core insulating layer extending in a first direction, an etch stop layer disposed on the core insulating layer, a channel layer extending along a sidewall of the core insulating layer and a sidewall of the etch stop layer, conductive patterns each surrounding the channel layer and stacked to be spaced apart from each other in the first direction, and an impurity region formed in an upper end of the channel layer.

High oxide film removal rate Shallow Trench Isolation (STI) chemical mechanical planarization (CMP) polishing compositions, methods, and systems of use therefore are provided. The CMP polishing composition comprises abrasives of ceria coated inorganic oxide particles, such as ceria-coated silica; and a chemical additive for providing a high oxide film removal rate. The chemical additive is a gelatin molecule possessing negative and positive charges on the same molecule.

A semiconductor device includes a bottom electrode, a top electrode, a sidewall spacer, and a data storage element. The sidewall spacer is disposed aside the top electrode. The data storage element is located between the bottom electrode and the top electrode, and includes a ferroelectric material. The data storage element has a peripheral region which is disposed beneath the sidewall spacer and which has at least 60% of ferroelectric phase. A method for manufacturing the semiconductor device and a method for transforming a non-ferroelectric phase of a ferroelectric material to a ferroelectric phase are also disclosed.

A polishing composition according to the present invention contains abrasive grains, a basic inorganic compound, an anionic water-soluble polymer, and a dispersing medium, in which a zeta potential of the abrasive grains is negative, an aspect ratio of the abrasive grains is 1.1 or less, in a particle size distribution of the abrasive grains obtained by a laser diffraction/scattering method, a ratio D90/D50 of a particle diameter D90 when an integrated particle mass reaches 90% of a total particle mass from a fine particle side to a particle diameter D50 when the integrated particle mass reaches 50% of the total particle mass from the fine particle side is more than 1.3, and the basic inorganic compound is an alkali metal salt.

A method for forming a semiconductor structure includes forming a hard mask layer over a target layer. The method also includes forming first mandrels over the hard mask layer. The method also includes forming a first opening in the first mandrels. The method also includes depositing a spacer layer over the hard mask layer and the first mandrels. The method also includes depositing a second mandrel material over the spacer layer. The method also includes planarizing the second mandrel material. The method also includes forming a second opening in the second mandrel material. The method also includes patterning and etching the second mandrel material to form second mandrels. The method also includes etching the spacer layer. The method also includes etching the hard mask layer and the target layer.

Non-planar semiconductor devices having doped sub-fin regions and methods of fabricating non-planar semiconductor devices having doped sub-fin regions are described. For example, a method of fabricating a semiconductor structure involves forming a plurality of semiconductor fins above a semiconductor substrate. A solid state dopant source layer is formed above the semiconductor substrate, conformal with the plurality of semiconductor fins. A dielectric layer is formed above the solid state dopant source layer. The dielectric layer and the solid state dopant source layer are recessed to approximately a same level below a top surface of the plurality of semiconductor fins, exposing protruding portions of each of the plurality of semiconductor fins above sub-fin regions of each of the plurality of semiconductor fins. The method also involves driving dopants from the solid state dopant source layer into the sub-fin regions of each of the plurality of semiconductor fins.

A method of performing a chemical mechanical planarization (CMP) process includes holding a wafer by a retainer ring attached to a carrier, pressing the wafer against a first surface of a polishing pad, the polishing pad rotating at a first speed, dispensing a slurry on the first surface of the polishing pad, and generating vibrations at the polishing pad.

A method includes forming a gate structure and an interlayer dielectric (ILD) layer over a substrate; selectively forming an inhibitor over the gate structure; performing an atomic layer deposition (ALD) process to form a dielectric layer over the ILD layer, wherein in the ALD process the dielectric layer has greater growing rate on the ILD than on the inhibitor; and performing an atomic layer etching (ALE) process to etch the dielectric layer until a top surface of the inhibitor is exposed, in which a portion of the dielectric layer remains on the ILD layer after the ALE process is complete.

A method includes forming a gate structure and an interlayer dielectric (ILD) layer over a substrate; selectively forming an inhibitor over the gate structure; performing an atomic layer deposition (ALD) process to form a dielectric layer over the ILD layer, wherein in the ALD process the dielectric layer has greater growing rate on the ILD than on the inhibitor; and performing an atomic layer etching (ALE) process to etch the dielectric layer until a top surface of the inhibitor is exposed, in which a portion of the dielectric layer remains on the ILD layer after the ALE process is complete.

A method 14 for the controlled removal of a protective layer 3 from a surface of a component 10, wherein the component comprises: a base body 1; an intermediate layer 2, which at least partially covers the base body; and said protective layer 3, which comprises an amorphous solid, in particular an amorphous nonmetal, in particular amorphous ceramic, and at least partially covers the intermediate layer;
wherein the method comprises the following steps: bringing 11 the protective layer 3 into contact with an etching or solvent medium 4; and removing 12 the protective layer 3 under the action of the etching or solvent medium 4 until the intermediate layer 2 is exposed;
and wherein the etching or solvent medium causes a first etching or dissolving speed of the protective layer and a second etching or dissolving speed of the intermediate layer and wherein the first etching or dissolving speed is greater than the second etching or dissolving speed. The invention furthermore relates to a method for replacing an old protective layer on a component, a method for operating a thin-film process facility, a component for use in a thin-film process facility, and a production method for the component.